upc eetac_1

Project P2 on the design of standard circuits


MUX_8 (type 74HCT151)

1. Specifications

Design a classic chip like the 74HCT151 using structural and behavioural approaches using only a single VHDL source file (flat design). The technology, whichever LS, S, AS, HC, HCT, F, etc. is not important, only the chip's functionality is considered.

Examine the Texas Instruments 74HCT151 datasheet and represent the symbol and truth table, renaming the inputs and outputs if necessary (discussed in class).  Because every company has its own way to name inputs/outputs and  organise their product datasheet (Nexperia, Toshiba/Renesas, ON semiconductor, etc.), in CSD we have to do the same, let us use our naming style and rewrite the truth table . 

Draw the sketch of a timing diagram to demonstrate how the circuit works for different inputs.

Fins similar products, like MUX_16, MUX_4, MUX_2 and demultiplexers.

MUX8_package

Fig. 1. Package and pin enumeration of a classic 74HCT151 chip. Because it is an inductry standard, whatever the vendor, the pin 12 will be always the input Ch7. 

Name the project MUX_8_prj and use the following EDA tools to implement it, selecting a target programmable chip (sPLD, CPLD or FPGA) from the list in the laboratory:

NOTE on the software: Altera Quartus II web edition v9.1 SP2 is installed in lab and Citrix computers because it runs faster than the new version Quartus Prime Lite and we can also configure the chips available in the lab.

NOTE on the software: The Xilinx ISE version is the 14.7, and we have installed it instead of the latest Vivado for the same reasons.

NOTE: SynplifyPro synthesiser is include in the Lattice software.

NOTE that the Xilinx ISim is already included in ISE Webpack

Learning materials and tutorials:

- Tutorial using a behavioural (high-level) description (truth table or algorithm) approach.

- Tutorial using a structural approach based on minimised equations (SoP / PoS).

- Tutorial using a structural approach based on canonical equations (minterms / maxterms).

 

2. Planning

Accordingly to the way we have discussed in class the specifications, in order to use a single-VHDL file project, let's follow two or three different plans:

A) The implementation and testing of a MUX_8 using a circuit's structure (a minimised equation)

B) The implementation and testing of a MUX_8 using a behavioural description.

C1) The implementation and testing of a MUX_8 using a hierarchical approach composed of a network of components of the same kind and other devices or logic.

This is a flow chart to explain the design process (pdf) (Visio).

And sure, there is a better method to be used in the following projects:

C2) A hierarchical MUX_8 using multiple VHDL files: a top design and components and signals. This project is fully demonstrated here as a P3 tutorial.

Thus, you can write the VHDL source file MUX_8.vhd using two or three different approaches and so be able to compare and discuss advantages and drawbacks of the different VHDL styles:

Plan A: structural (logic equations) 

Plan B: behavioural plan: (Truth table, or algorithms)

1.- Use a VHDL description of a minimised (SoP or PoS) logic equations. (Why the canonical maxterms or minterms are not suitable here?)

1. - Use a VHDL description of the chip truth table.

2.- Projects and files must be located in cooperative group shared folders:

<drive>/CSD/P2/MUX_8A/(files).

2. Projects and files must be located in cooperative group shared folders:

<drive>/CSD/P2/MUX_8B/(files).

3.- Find a similar VHDL circuit with and architecture that uses logic equations to copy and adapt.

3.- Find a similar VHDL circuit with an architecture that corresponds to a truth table to copy and adapt.

4.- Use the Minilog.exe (or Logic Friday)application to get the simplest PoS or SoP equation of the truth table, or instead, deduce the equation inspecting the truth table. 

4.- Use  signals to connect ports and the inner truth table statement. Draw an schematic and translate it to VHDL. 

There is a third plan:

Plan C1: Hierarchical in a single file connecting smaller devices of the same kind and other circuits or logic

1.- Invent an internal architecture composed of several building blocs interconnected.

2.- Use a VHDL description of every block (equations/truth tables or algorithms, etc.) connecting them using signals.

3.- Find a similar VHDL circuit with a similar architecture to copy and adapt.

4.- Projects and files must be located in cooperative group shared folders:

<drive>/CSD/P2/MUX_8C1/(files).

NOTE: Most of the projects of this CSD course are organised and solved in a similar fashion, thus, once you've become aware of it, and have some practice, it'll be something familiar to you. Furthermore, you'll be able to assess yourself and so have a pretty good idea of your grades before a formal reviewing and even without the intervention of your instructor. 

3. Development

NOTE: Do not write VHDL code without the corresponding schematic/equation/diagram/flow chart/algorithm from the previous planning section. Here in CSD, the VHDL source file is always a direct translation of your sketches represented in pen-and-paper.

1.- This is the description of the entity accordingly to the CSD input and output naming agreed in class:

MUX_8 entity

Use in CSD the Scriptum text editor, a very convenient free tool for writing VHDL files from the company HDL Works. Another similar product that can suit you very well is Notepath++ (it also contains an spelling checker plug-in).  Both tools are available in the lab computers and Citrix.

 

2.- Now, to develop the architecture, let's pay attention to the Plan A, Plan B or Plan C1. For example:

Plan A: structural  

Plan B: behavioural

1.- Deduce the circuit equations using Boole's Algebra or Minilog.exe or Logic Friday. 

1. - Write a VHDL file MUX_8.vhd that contains an architecture based on the truth table or an algorithmic description of the circuit.

2.- Write down the VHDL file MUX_8.vhd which contains an architecture of the circuit based on equations.

2. Start an EDA tool project for a CPLD/FPGA chip MUX_8_prj and obtain the synthesised circuit. It is a project of only one VHDL file (flat design).

3.-Start an EDA tool project for a CPLD/FPGA chip MUX_8_prj and obtain the synthesised circuit. It is a project of only one VHDL file (flat design).

4.- Represent and analyse the computer generated RTL and technology views or schematics of the circuits.

3.- Represent and analyse the computer generated RTL and technology views or schematics of the circuits.

 

Plan C1: hierarchical (Connecting smaller components of the same kind and other chips if necessary) 

1.- Write a single VHDL file MUX_8.vhd

2.- Start an EDA tool project for a CPLD/FPGA chip MUX_8_prj and obtain the synthesised circuit. It is a project of only one VHDL file (flat design).
3.- Draw and discuss the computer generated RTL and technology views or schematics of the circuits.

 

If you follow the Plan A, find structural equations and stuff here in this similar example based on the design of a Dual_MUX4. You will require the files MUX_8.tbl, MUX_8.min to find a simplified equation.

ON_Semiconductor

Fig. 2. This RTL schematic of a MUX_8 is from the ON_semiconductor datasheet. You project has to generate something similar.

And if you follow the Plan B, here you are three versions (1), (2) and (3) of a MUX_4 from the truth table itself (behavioural) that you can easily adapt to be a MUX_8. Multiplexers are basic building blocks that are used everywhere in digital system design. For example, here in these former guided Problem 3.9 or Problem 3.10, you can see how multiplexers are used as one of the many components in the subsystem.

As always, every description style has its advantages and drawbacks. In our case, the VHDL description must be agreed by all the cooperative team and even all the class, so that you better learn from each other and correct easily the mistakes when transferring schematics to VHDL.

Some results (from class discussion of the Plan C1):

4. Testing

To test either design approach (behavioural or structural), use the same test bench (we have the same entity with different internal architectures).

Timing diagram preferred colour schemes:

- Altera Quartus II: This a colour scheme to be able to print logic analyser results in a white back colour instead of the default black.

- Xilinx ISE colour scheme (ISim preferences).

- The ActiveHDL colour scheme is already configured by default.

1.- Start an EDA VHDL simulator project MUX_8_sim_prj and verify the Device-Under-Test (DUT) using a VHDL simulator test bench. The name of the file will depend on the tool (MUX_8.vht for Altera Quartus II or Lattice ispLEVER Classic or Diamond, MUX_8_tb.vhd for Xilinx ISE.

2.- Start the simulation process with only a few input vectors (from the timing diagram sketch in the specifications) to see if the whole simulation process works and you are able to see input and output signals activity. 

3.- Verify applying sufficient test vector that the device works as expected (verify how the information of each channel is selected). Print the timing diagram screen and add comments on the signals to show how the device works.

 

Some results (from class discussion):

 

5. Report

Because this is the first VHDL project, special attention has to be paid in annotating all the necessary steps to carry on the design process or flow of a circuit using VHDL synthesis and simulation tools. This design flow will be repeated once and again from this P2 to P8.

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources. 

 

6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works. 

 

Other similar projects on standard combinational logic circuits

- Binary decoder and demultiplexer, priority encoder, hexadecimal (or BCD) to 7 segment decoder (see the tutorials above related to the classic 74LS49), dice decoder, etc.

- This is a similar project to design a Dual_MUX_4, the functionality of the classic chip 74LS153 multiplexer.

- Arithmetic circuit in P3 and P4.

Other materials of interest

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