upc eetac_1

P1

Project P2 on standard logic circuits: multiplexer, decoder, etc.

P3


MUX_8 (type 74HCT151)

Single-file VHDL (flat) design (Plan A or Plan B)

1. Specifications

Design a MUX_8 in a PLD target chip with specifications similar to a classic 74HCT151 chip. The technology, whichever it is LS, S, AS, HC, HCT, F, etc. is not important because it wil be configured in a PLD, and so, only the chip's functionality is considered.  Propose several alternative architectures (structural, behavioural and hierarchical).

Examine the Texas Instruments 74HCT151 datasheet and represent the symbol and truth table, renaming the inputs and outputs in this way. Draw the sketch of a timing diagram to demonstrate how the circuit works for different inputs and so, be able to translate it later to VHDL as a testbench.

Find and study similar products, like MUX_16, MUX_4, MUX_2 and also demultiplexers.

MUX8_package

Fig. 1. Package and pin enumeration of a classic 74HCT151 chip. Because it is an industry standard, whatever the name given to the pins by the vendor, the pin 12 will be always the input Ch7, an so the same with all the other pins. 

We have to interpret and rename the pins because every company has its own way to name inputs/outputs and organise their product datasheet (Nexperia, Toshiba/Renesas, ON semiconductor, etc.); thus in CSD we have decided to use our own naming style and rewrite the truth table accordingly. 

Name the project MUX_8_prj and use one of the following EDA tools to implement it, selecting a target programmable chip (sPLD, CPLD or FPGA) from the training boards in the laboratory:

  • CAD- EDA project tools and circuit synthesisers: Lattice ispLEVER Classic - Diamond  / Intel-Altera Quartus II / Xilinx ISE Webpack

NOTE #1 on the software: Intel-Altera Quartus II web edition v9.1 SP2 is installed in lab and in our virtual desktopx computers because it runs faster than the new version Quartus Prime Lite and we can configure the chips available in the lab.

NOTE #2 on the software: The Xilinx ISE version is the 14.7, and we have installed it instead of the latest Vivado for the same reasons explained in Note #1.

NOTE #3: SynplifyPro synthesiser is include in the Lattice software.

  • CAD - EDA VHDL simulators  ActiveHDL Lattice Edition / ModelSim Altera Starter Edition / Xilinx ISim

NOTE #4: Xilinx ISim is already included in ISE Webpack

In CSD edit VHDL and C text source files using the Notepath++ enriched text editor (it also contains an spelling checker plug-in). Another similar product that can suit you very well is  the Scriptum text editor, a very convenient free tool for writing VHDL files from the company HDL Works.

Learning materials:

- Some theory on basics of standard logic circuits: multiplexers, demultiplexers, encoders, decoders, etc.

- This is a similar project to design a Dual_MUX4: the functionality of the classic chip 74LS153 multiplexer.

- Tutorial (Plan B) of a Dec_3_8.

- Tutorial (plan A) HEX to 7 SEG decoder (type 74LS47). Using a structural approach based on minimised equations (SoP / PoS).

- Tutorial (plan B) HEX to 7 SEG decoder (type 74LS47). Using a behavioural (high-level) description (truth table or algorithm) approach.

- The concept of incomplete logic functions (truth table outputs with don't care terms).

 

2. Planning

This is the general panorama (pdf, Visio), a concept map representing the important terms and definitions to design any kind of circuit in CSD. 

This is a flow chart (Visio) to explain the main concepts involved in the VHDL design flow process.

Accordingly to the way we have discussed in class the specifications, in order to implement the MUX_8 in a single-VHDL file project, let's follow three alternative plans:

 

Plan A: structural  

1.- Use a VHDL description of a minimised SoP or PoS logic equations. (Why the canonical maxterms or minterms are not recommended in this plan?). Find the equations running minilog. The implementation of a MUX_8 using a circuit's structure, for example a minimised equation derived from Minilog.

2.- Save the project here:                                         

<drive>/CSD/P2/MUX_8A/(files)

3.- Find a similar VHDL circuit with an architecture that uses logic equations to copy and adapt.

4.- Write down the VHDL file MUX_8.vhd which contains an architecture of the circuit based on equations.

 

Plan B: behavioural

1. - Translate the truth table into an algorithms or flow chart like in version (1) or (3), or instead, into an schematics such in version (2).

2. - Save project files here (each behavioural description becomes a complete diffeernt project):

<drive>/CSD/P2/MUX_8B1/(files)

<drive>/CSD/P2/MUX_8B2/(files)

<drive>/CSD/P2/MUX_8B3/(files).

3.- Find a similar VHDL circuit with an architecture that corresponds to a truth table or algorithm to copy and adapt. Translate your algorith, flow chart or schematic into VHDL in a single file.

 

Plan C1: hierarchical in a single file connecting smaller devices of the same kind and other circuits or logic

1.- Invent an internal architecture composed of several building blocs interconnected together. Analyse the Fig. 2, this is the implementation of a MUX_8 using a hierarchical approach composed of a network of components of the same kind and other devices or logic in a single VHDL file (flat)

2.- Use a VHDL description of every block (equations/truth tables or algorithms, etc.) connecting them using signals.

3.- Find a similar VHDL circuit with a similar structural architecture to copy and adapt.

4.- Save project files here: 

<drive>/CSD/P2/MUX_8C1/(files).

Plan_C1

Fig. 2. This is an architecture proposed for the MUX_8 organised as a hierarchical design containing components of the same kind (MUX_2, etc., logic gates and wires (signals):

  • Plan C1) place them all in a single VHDL file (not recommended)

  • Plan C2) place the circuit in several files organised hierarchically  (recommended and preferred method in CSD) . 

 

And sure, there is a multiple-VHDL file method for conceiving the MUX_8:

Plan C2) the same Fig. 2. The implementation of a MUX_8 using a hierarchical approach composed of a network of components of the same kind and other devices or logic in several VHDL files: a top design (MUX_8.vhd) and components (MUX_2.vhd, MUX4_vhd) and signals K, P, Q. This project is fully demonstrated here as a P3 tutorial.

Thus, you can write the VHDL source file MUX_8.vhd using different approaches and be able to compare and discuss advantages and drawbacks of the different VHDL styles:

NOTE: Most of the projects of this CSD course are organised and solved in a similar fashion, thus, once you've become aware of it, and have some practice, it'll be something familiar to you. Furthermore, you'll be able to assess yourself and so have a pretty good idea of your grades before a formal reviewing and even without the intervention of your instructor. 

3. Development

NOTE: Do not write VHDL code without the corresponding schematic / equation / diagram / flow chart / algorithm from the previous planning section. Here in CSD, the VHDL source file is always a direct translation of your sketches represented in pen-and-paper.

1.- Write the VHDL files. The entity is the same for all the projects since it is related to the symbol:

The entity

If you follow the Plan A, find structural equations and stuff here in this similar example based on the design of a Dual_MUX4. You will require the files MUX_8.tbl, MUX_8.min to find a simplified equation. This is a possible MUX_8,vhd.

 ON_Semiconductor

Fig. 3. This RTL schematic of a MUX_8 is from the ON Semiconductor datasheet. You project has to generate something similar when following plan A or plan C1.

If you follow the Plan B, here you are three versions (1), (2) and (3) of a MUX_4 from the truth table itself (behavioural) that you can easily adapt to be your MUX_8.

And if you follow the Plan C1, here you are the MUX_8.vhd file, the tranlation of the architecture shown in Fig. 2. This is an example RTL view to be compared with Fig. 3.  

 

2.- Synthesise the circuit's architecture accordingly to the plans A, B or C1:

Start an EDA tool project for a sPLD/CPLD/FPGA chip MUX_8_prj and obtain the synthesised circuit. It is a project consisting of a single VHDL file (flat design).

Print, analyse and comment the computer generated RTL and technology views or schematics of the circuits.

 

Discuss the advantages and drawbacks of each development. Compare specifically the RTL and technology views of the three methodologies.

 

4. Testing

To test the solution whatever it is from plan A, plan B or plan C1, use the same test bench because even if you have different architectures, we use always the same entity definition. This is an example of a simple test bench MUX_8_tb.vhd where the inputs have been stimulated with logic values.

These are the timing diagram preferred colour schemes (already configured) :

- Altera Quartus II: This a colour scheme to be able to print logic analyser results in a white back colour instead of the default black.

- Xilinx ISE colour scheme (ISim preferences).

- The ActiveHDL colour scheme is already configured by default.

1.- Start an EDA VHDL simulator project to verify the Device-Under-Test (DUT) using a VHDL simulator test bench. The name of the file will be: MUX_8_tb.vhd (if the tool generates a MUX_8.vht, simply rename it).

2.- Start the simulation process with only a few input vectors (from the timing diagram sketch in the specifications) to see if the whole simulation process works and you are able to see input and output signals activity. 

3.- Verify applying sufficient test vector that the device works as expected (verify how the information of each channel is selected). Print the timing diagram screen and add comments on the signals to show how the device works.

Some results (from class discussion):

test example

Fig. 4. Example of a timing diagram produced by the simulator with some mandatory comments and discussion on the way the circuit works.

5. Report

Because this is the first VHDL project, special attention has to be paid in annotating all the necessary steps to carry on the design process or flow of a circuit using VHDL synthesis and simulation tools. This design flow will be repeated once and again from this P2 to P8. 

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources. 

 

6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works. More notes in this lesson about target chips sPLD, CPLD and FPGA. 

 

Other similar projects on combinational logic circuits

- Encoders, demultiplexers, code converters, dice decoder, wind direction encoder, etc.

- This file can be used to copy and adapt to translate an encoder truth table to VHDL (plan B).

Other materials of interest

- Q & A.

- Exams, questions, problems and projects

- Standard arithmetic circuit in P3 and P4.

- Multiplexers are basic building blocks that are used everywhere in digital system design. For example, here in these former guided Problem 3.9 or Problem 3.10, you can see how multiplexers are used as one of the many components in the subsystem.