upc eetac_1


Project P5 on 1-bit memory cells: latches and flip-flops


Latch type 74LS279A, Flip-flop type HEF4027B, synchronicity (CLK)

and finite state machines (FSM)

1. Specifications (understanding the problem)

A. Design a synchronous 1-bit memory cell type JK flip-flop (JK_FF) using the FSM strategy. It can be used to store/save/write/register a 1-bit of information, as a frequency divider by 2 or as the basic block to implement digital counters and data registers. As you see in Fig. 1 function table, at the CLK's rising edge, the output value will depend on the inputs J and K and also on the previously stored value. 


Fig. 1. Symbol, function table and example timing diagram of a JK flip-flop. Clear direct (CD) is the asynchronous reset. Be aware on how the J and K inputs has to be stable before the sampling edge, because if not, the output is unpredictable. (Visio).

Timing diagram example 

B. Perform a gate-level simulation of the circuit to measure its CLK-to-output time (tCO) and thus, the maximum frequency of operation for a given target chip.

Fig. 2. Flip-flop setup, hold and clock-to-output timing parameters. Source. For a given technology, tCO determines the minimum CLK period, as the outputs must be stabilised before applying another CLK rising edge.


Learning materials:

- As the first exercise, this is the deduction of the RS_latch from logic gates. 

. The basic 1-bit memory devices.

- Tutorial on the analysis of an asynchronous circuit, the strategy that is unreliable. All our circuits will be synchronous following the FSM architecture.

- Tutorial on how to design the data flip-flop (D_FF) containing the CSD VHDL description based on a single-file behavioural approach (as in P2 plan B, the algorithm, in this case the function table). This device is used as the memory cell in the FSM state register. 

- Tutorial on how to design a toggle flip-flop (T_FF) using our FSM architecture. Therefore, you can design the JK or the RS flip-flops or any other sequential circuit in P6, P7 and P8 using the same procedure.


2. Planning (devising a strategy to solve the problem)

As always, the aim of the planning section is to obtain a schematic or flow chart that can be automatically translated to VHDL.

First of all, let's study the basics of the 1-bit memory devices (asynchronous latches and synchronous flip-flops). How are they designed? How do they work? Now, it is right continuing with the design of a D_FF so that you get an idea of what is the CLK and how it works.

And, once the theory understood, let us apply the FSM methodology to build and test the JK_FF as a single file project. This procedure with slight variations is going to be repeated in all the FSM projects.

1) Figure out the state diagram. Number of states and conditions of transitions. Write the outputs at each state in parenthesis and using another colour.

2) Particularise the general FSM topology in Fig. 3 to this problem and answer these questions:

a) State register based on D_FF. Number of bits for the current and next state coding (r). [ r = number of states if one-hot; r = (1/log 2)·log (number of states) if binary or Gray]. How many 1-bit registers (D_FF) will the circuit contain?

b) To which block is connected every input and output port?


Fig. 3. Topology and description of the FSM used in CSD. (Visio).

3) Draw the state register. We'll use always the same VHDL code description.

4) Output logic (CC2), required to calculate the outputs at each state. Truth table, and flow chart if a behavioural description is used, which is normally the best idea because in this way the Boolean algebra is left to the synthesiser.

5) Next state logic (CC1), required to calculate the next state to go after the CLK's rising edge. Truth table, and flow chart using a behavioural description, which is normally the best idea because the equations are left to the synthesiser.

6) Project folder location and file name (JK_FF.vhd):



3. Development (carrying out the plan)

Write down the VHDL file corresponding the T_FF after having translated the flow charts of the CC1 and CC2 and copied the state register. Copy and adapt a previous example, for instance the T_FF

The name of the source file is JK_FF.vhd. Run the EDA tool to synthesise the circuit and print and comment the RTL schematic. Check the number of registers (D_FF) used in the target chip. In this simple example, the answer has to be a single D_FF register.


4. Testing (and looking back and forward...)

Start the test bench template and add the CLK and inputs activity translating the timing diagram in Fig.1. Thus, to test sequential systems at least two stimulus processes will be required: one process for the CLK and another one for all the other input signals (Fig. 4). Make all the timing relative to the CLK_Period constant, which is the equivalent in Chapter 2 to the Chapter 1 constant Min_Pulse.

The test bench file name may be: JK_FF_tb.vhd.

4.1) Functional simulation. Run the EDA VHDL tool and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms.

4.2. Gate-level simulation. Run the EDA VHDL tool using the same test bench and measure the CLK to output delays and the maximum frequency of operation for a given CPLD or FPGA target chip.


Fig. 4. VHDL testbench. Let's use different processes to drive the inputs and the CLK.


5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources


6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.

Other similar projects on sequential circuits

- Here you are some guided exercises (1) and (2) on sequential systems that will give you an idea of the possibilities and applications of sequential designs.

- Exams, questions, problems and projects. The sequence of P5 problems follows approximately how this topic is discussed in class.


Other materials of interest

- Flip-flops are the basic building block of digital systems. They are fully documented everywhere.

- For instance, the Lattice Semiconductor CPLD ispMACH4128V TQFP100 contains 128 macrocells. Each macrocell (Fig. 5) includes a configurable register D_FF along with some logic and control functions.

Fig. 5. Lattice Semiconductor ispMACH macrocell