ispLEVER Classic 2.0.00.17.20.15 Fitter Report File
Copyright(C), 1992-2012, Lattice Semiconductor Corporation
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Project_Summary
Project Name : matrix_encoder_16key_top
Project Path : L:\CSD\P6\ispMACH4128V
Project Fitted on : Mon Apr 24 11:53:45 2017
Device : M4128_64
Package : 100
GLB Input Mux Size : 19
Available Blocks : 8
Speed : -10
Part Number : LC4128V-10T100I
Source Format : Pure_VHDL
Project 'matrix_encoder_16key_top' Fit Successfully!
Compilation_Times
Prefit Time 0 secs
Load Design Time 0.05 secs
Partition Time 0.02 secs
Place Time 0.00 secs
Route Time 0.00 secs
Total Fit Time 00:00:01
Design_Summary
Total Input Pins 6
Total Logic Functions 32
Total Output Pins 20
Total Bidir I/O Pins 0
Total Buried Nodes 12
Total Flip-Flops 8
Total D Flip-Flops 8
Total T Flip-Flops 0
Total Latches 0
Total Product Terms 104
Total Reserved Pins 0
Total Locked Pins 26
Total Locked Nodes 0
Total Unique Output Enables 0
Total Unique Clocks 1
Total Unique Clock Enables 0
Total Unique Resets 1
Total Unique Presets 1
Fmax Logic Levels 1
Device_Resource_Summary
Device
Total Used Not Used Utilization
-----------------------------------------------------------------------
Dedicated Pins
Clock/Input Pins 4 1 3 --> 25
Input-Only Pins 6 0 6 --> 0
I/O / Enable Pins 2 2 0 --> 100
I/O Pins 62 23 39 --> 37
Logic Functions 128 32 96 --> 25
Input Registers 64 0 64 --> 0
GLB Inputs 288 72 216 --> 25
Logical Product Terms 640 88 552 --> 13
Occupied GLBs 8 6 2 --> 75
Macrocells 128 32 96 --> 25
Control Product Terms:
GLB Clock/Clock Enables 8 0 8 --> 0
GLB Reset/Presets 8 0 8 --> 0
Macrocell Clocks 128 0 128 --> 0
Macrocell Clock Enables 128 0 128 --> 0
Macrocell Enables 128 0 128 --> 0
Macrocell Resets 128 0 128 --> 0
Macrocell Presets 128 0 128 --> 0
Global Routing Pool 220 21 199 --> 9
GRP from IFB .. 5 .. --> ..
(from input signals) .. 5 .. --> ..
(from output signals) .. 0 .. --> ..
(from bidir signals) .. 0 .. --> ..
GRP from MFB .. 16 .. --> ..
----------------------------------------------------------------------
<Note> 1 : The available PT is the product term that has not been used.
<Note> 2 : IFB is I/O feedback.
<Note> 3 : MFB is macrocell feedback.
GLB_Resource_Summary
# of PT
--- Fanin --- I/O Input Macrocells Macrocells Logic clusters
Unique Shared Total Pins Regs Used Inaccessible available PTs used
-------------------------------------------------------------------------------------------
Maximum
GLB 36 *(1) 8 -- -- 16 80 16
-------------------------------------------------------------------------------------------
GLB A 4 9 13 7/8 0 7 0 9 16 7
GLB B 4 5 9 0/8 0 3 0 13 6 3
GLB C 2 7 9 1/8 0 3 0 13 6 3
GLB D 6 5 11 0/8 0 3 0 13 6 3
-------------------------------------------------------------------------------------------
GLB E 0 0 0 0/8 0 0 0 16 0 0
GLB F 6 9 15 8/8 0 8 0 8 19 7
GLB G 0 0 0 0/8 0 0 0 16 0 0
GLB H 3 12 15 7/8 0 8 0 8 35 9
-------------------------------------------------------------------------------------------
TOTALS: 25 47 72 23/64 0 32 0 96 88 32
<Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB.
<Note> 2 : Four rightmost columns above reflect last status of the placement process.
GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell
Clk/CE Rst/Pr | Clock CE Enable Reset Preset
------------------------------------------------------------------------------
Maximum
GLB 1 1 16 16 16 16 16
==============================================================================
GLB A 0 0 0 0 0 0 0
GLB B 0 0 0 0 0 0 0
GLB C 0 0 0 0 0 0 0
GLB D 0 0 0 0 0 0 0
------------------------------------------------------------------------------
GLB E 0 0 0 0 0 0 0
GLB F 0 0 0 0 0 0 0
GLB G 0 0 0 0 0 0 0
GLB H 0 0 0 0 0 0 0
------------------------------------------------------------------------------
<Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB.
Optimizer_and_Fitter_Options
Pin Assignment : Yes
Group Assignment : No
Pin Reservation : No
@Ignore_Project_Constraints :
Pin Assignments : No
Keep Block Assignment --
Keep Segment Assignment --
Group Assignments : No
Macrocell Assignment : No
Keep Block Assignment --
Keep Segment Assignment --
@Backannotate_Project_Constraints
Pin Assignments : No
Pin And Block Assignments : No
Pin, Macrocell and Block : No
@Timing_Constraints : No
@Global_Project_Optimization :
Balanced Partitioning : Yes
Spread Placement : Yes
Note :
Pack Design :
Balanced Partitioning = No
Spread Placement = No
Spread Design :
Balanced Partitioning = Yes
Spread Placement = Yes
@Logic_Synthesis :
Logic Reduction : Yes
Node Collapsing : FMAX
Fmax_Logic_Level : 1
D/T Synthesis : Yes
XOR Synthesis : Yes
Max. P-Term for Collapsing : 16
Max. P-Term for Splitting : 80
Max Symbols : 24
@Utilization_options
Max. % of Macrocells used : 100
@Usercode (HEX)
@IO_Types Default = LVCMOS18 (2)
@Output_Slew_Rate Default = FAST (2)
@Power Default = HIGH (2)
@Pull Default = PULLUP_UP (2)
@Fast_Bypass Default = None (2)
@ORP_Bypass Default = None
@Input_Registers Default = None (2)
@Register_Powerup Default = None
Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
Bidir and Buried Signal Lists.
Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal|
Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name
-------------------------------------------------------------------------------------
1 | GND | - | | | | |
2 | TDI | - | | | | |
3 | I_O | 0 |B0 | | | |
4 | I_O | 0 |B2 | | | |
5 | I_O | 0 |B4 | | | |
6 | I_O | 0 |B6 | | | |
7 |GNDIO0 | - | | | | |
8 | I_O | 0 |B8 | | | |
9 | I_O | 0 |B10 | | | |
10 | I_O | 0 |B12 | | | |
11 | I_O | 0 |B13 | | | |
12 | IN0 | 0 | | | | |
13 |VCCIO0 | - | | | | |
14 | I_O | 0 |C14 | | | |
15 | I_O | 0 |C12 | | | |
16 | I_O | 0 |C10 | | | |
17 | I_O | 0 |C8 | * |LVCMOS18 | Input |CD
18 |GNDIO0 | - | | | | |
19 | I_O | 0 |C6 | | | |
20 | I_O | 0 |C5 | | | |
21 | I_O | 0 |C4 | | | |
22 | I_O | 0 |C2 | | | |
23 | IN1 | 0 | | | | |
24 | TCK | - | | | | |
25 | VCC | - | | | | |
26 | GND | - | | | | |
27 | IN2 | 0 | | | | |
28 | I_O | 0 |D13 | | | |
29 | I_O | 0 |D12 | | | |
30 | I_O | 0 |D10 | | | |
31 | I_O | 0 |D8 | | | |
32 |GNDIO0 | - | | | | |
33 |VCCIO0 | - | | | | |
34 | I_O | 0 |D6 | | | |
35 | I_O | 0 |D4 | | | |
36 | I_O | 0 |D2 | | | |
37 | I_O | 0 |D0 | | | |
38 |INCLK1 | 0 | | | | |
39 |INCLK2 | 1 | | | | |
40 | VCC | - | | | | |
41 | I_O | 1 |E0 | | | |
42 | I_O | 1 |E2 | | | |
43 | I_O | 1 |E4 | | | |
44 | I_O | 1 |E6 | | | |
45 |VCCIO1 | - | | | | |
46 |GNDIO1 | - | | | | |
47 | I_O | 1 |E8 | | | |
48 | I_O | 1 |E10 | | | |
49 | I_O | 1 |E12 | | | |
50 | I_O | 1 |E14 | | | |
51 | GND | - | | | | |
52 | TMS | - | | | | |
53 | I_O | 1 |F0 | * |LVCMOS18 | Output|R_LEDs_0_
54 | I_O | 1 |F2 | * |LVCMOS18 | Output|R_LEDs_1_
55 | I_O | 1 |F4 | * |LVCMOS18 | Output|R_LEDs_2_
56 | I_O | 1 |F6 | * |LVCMOS18 | Output|R_LEDs_3_
57 |GNDIO1 | - | | | | |
58 | I_O | 1 |F8 | * |LVCMOS18 | Output|D_LEDs_0_
59 | I_O | 1 |F10 | * |LVCMOS18 | Output|D_LEDs_1_
60 | I_O | 1 |F12 | * |LVCMOS18 | Output|D_LEDs_2_
61 | I_O | 1 |F13 | * |LVCMOS18 | Output|D_LEDs_3_
62 | IN3 | 1 | | | | |
63 |VCCIO1 | - | | | | |
64 | I_O | 1 |G14 | | | |
65 | I_O | 1 |G12 | | | |
66 | I_O | 1 |G10 | | | |
67 | I_O | 1 |G8 | | | |
68 |GNDIO1 | - | | | | |
69 | I_O | 1 |G6 | | | |
70 | I_O | 1 |G5 | | | |
71 | I_O | 1 |G4 | | | |
72 | I_O | 1 |G2 | | | |
73 | IN4 | 1 | | | | |
74 | TDO | - | | | | |
75 | VCC | - | | | | |
76 | GND | - | | | | |
77 | IN5 | 1 | | | | |
78 | I_O | 1 |H13 | * |LVCMOS18 | Output|GS
79 | I_O | 1 |H12 | * |LVCMOS18 | Output|segments_5_
80 | I_O | 1 |H10 | * |LVCMOS18 | Output|segments_4_
81 | I_O | 1 |H8 | * |LVCMOS18 | Output|segments_6_
82 |GNDIO1 | - | | | | |
83 |VCCIO1 | - | | | | |
84 | I_O | 1 |H6 | * |LVCMOS18 | Output|segments_1_
85 | I_O | 1 |H4 | * |LVCMOS18 | Output|segments_3_
86 | I_O | 1 |H2 | * |LVCMOS18 | Output|segments_0_
87 | I_O/OE| 1 |H0 | * |LVCMOS18 | Output|segments_2_
88 |INCLK3 | 1 | | | | |
89 |INCLK0 | 0 | | * |LVCMOS18 | Input |OSC_CLK_in
90 | VCC | - | | | | |
91 | I_O/OE| 0 |A0 | * |LVCMOS18 | Input |Columns_0_
92 | I_O | 0 |A2 | * |LVCMOS18 | Input |Columns_1_
93 | I_O | 0 |A4 | * |LVCMOS18 | Input |Columns_2_
94 | I_O | 0 |A6 | * |LVCMOS18 | Input |Columns_3_
95 |VCCIO0 | - | | | | |
96 |GNDIO0 | - | | | | |
97 | I_O | 0 |A8 | * |LVCMOS18 | Output|Rows_0_
98 | I_O | 0 |A10 | * |LVCMOS18 | Output|Rows_1_
99 | I_O | 0 |A12 | * |LVCMOS18 | Output|Rows_2_
100 | I_O | 0 |A14 | * |LVCMOS18 | Output|Rows_3_
-------------------------------------------------------------------------------------
<Note> GLB Pad : This notation refers to the GLB I/O pad number in the device.
<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
<Note> Pin Type :
ClkIn : Dedicated input or clock pin
CLK : Dedicated clock pin
I_O : Input/Output pin
INP : Dedicated input pin
JTAG : JTAG Control and test pin
NC : No connected
Input_Signal_List
Input
Pin Fanout
Pin GLB Type Pullup Signal
---------------------------------------------
17 C I/O 3 -BCD---- Up CD
91 A I/O 6 ABCD-F-H Up Columns_0_
92 A I/O 6 ABCD-F-H Up Columns_1_
93 A I/O 6 ABCD-F-H Up Columns_2_
94 A I/O 6 ABCD-F-H Up Columns_3_
89 -- INCLK -------- Up OSC_CLK_in
---------------------------------------------
Output_Signal_List
I C P R P O Output
N L Mc R E U C O F B Fanout
Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal
----------------------------------------------------------------------------
58 F 7 3 3 1 COM 1 -------H Fast Up D_LEDs_0_
59 F 8 3 5 1 COM 1 -------H Fast Up D_LEDs_1_
60 F 6 3 2 1 COM 1 -------H Fast Up D_LEDs_2_
61 F 7 3 5 1 COM 1 -------H Fast Up D_LEDs_3_
78 H 4 - 1 1 COM -------- Fast Up GS
53 F 2 - 1 1 COM -------- Fast Up R_LEDs_0_
54 F 2 - 1 1 COM -------- Fast Up R_LEDs_1_
55 F 2 - 1 1 COM -------- Fast Up R_LEDs_2_
56 F 2 - 1 1 COM -------- Fast Up R_LEDs_3_
97 A 2 - 1 1 COM -------- Fast Up Rows_0_
98 A 2 - 1 1 COM -------- Fast Up Rows_1_
99 A 2 - 1 1 COM -------- Fast Up Rows_2_
100 A 2 - 1 1 COM -------- Fast Up Rows_3_
86 H 12 4 5 1 COM -------- Fast Up segments_0_
84 H 10 4 10 2 COM -------- Fast Up segments_1_
87 H 4 4 3 1 COM -------- Fast Up segments_2_
85 H 8 4 4 1 COM -------- Fast Up segments_3_
80 H 11 4 4 1 COM -------- Fast Up segments_4_
79 H 7 4 4 1 COM -------- Fast Up segments_5_
81 H 7 4 4 1 COM -------- Fast Up segments_6_
----------------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
FP = Fast path used
OBP = ORP bypass used
Bidir_Signal_List
I C P R P O Bidir
N L Mc R E U C O F B Fanout
Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal
-----------------------------------------------------------------------
-----------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
FP = Fast path used
OBP = ORP bypass used
Buried_Signal_List
I C P R P Node
N L Mc R E U C I F Fanout
Mc GLB P LL PTs S Type E S P E R P Signal
-----------------------------------------------------------------------
10 D 7 1 2 1 DFF * R 5 AB-D-F-H Chip1_current_state_0_
5 D 7 1 2 1 DFF * R 4 AB-D-F-- Chip1_current_state_1_
10 C 7 1 2 1 DFF * R 5 A-CD-F-H Chip1_current_state_2_
5 B 7 1 2 1 DFF * R 4 A-CD-F-- Chip1_current_state_3_
2 D 7 1 2 1 DFF * R 5 AB-D-F-H Chip1_current_state_4_
5 C 7 1 2 1 DFF * R 4 AB-D-F-- Chip1_current_state_5_
2 C 7 1 2 1 DFF * R 4 A-C--F-H Chip1_current_state_6_
2 B 7 1 2 1 DFF * S 3 A-C--F-- Chip1_current_state_7_
7 A 9 - 4 1 COM 2 -----F-H chip1_data_1_0_0__n
10 B 4 - 2 1 COM 1 A------- chip1_n_133_n
5 A 8 - 5 1 COM 2 -----F-H chip1_n_141_i_n
12 A 8 - 3 1 COM 2 -----F-H chip1_n_98_0_n
-----------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
IR = Input register
FP = Fast path used
OBP = ORP bypass used
PostFit_Equations
Chip1_current_state_0_.D = !( Columns_3_ & Columns_2_ & Columns_1_
& Columns_0_
# !Chip1_current_state_1_.Q & !Chip1_current_state_0_.Q ) ; (2 pterms, 6 signals)
Chip1_current_state_0_.C = OSC_CLK_in ; (1 pterm, 1 signal)
Chip1_current_state_0_.AR = CD ; (1 pterm, 1 signal)
Chip1_current_state_1_.D = Columns_3_ & Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_3_.Q
# Columns_3_ & Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_2_.Q ; (2 pterms, 6 signals)
Chip1_current_state_1_.C = OSC_CLK_in ; (1 pterm, 1 signal)
Chip1_current_state_1_.AR = CD ; (1 pterm, 1 signal)
Chip1_current_state_2_.D = !( Columns_3_ & Columns_2_ & Columns_1_
& Columns_0_
# !Chip1_current_state_3_.Q & !Chip1_current_state_2_.Q ) ; (2 pterms, 6 signals)
Chip1_current_state_2_.C = OSC_CLK_in ; (1 pterm, 1 signal)
Chip1_current_state_2_.AR = CD ; (1 pterm, 1 signal)
Chip1_current_state_3_.D = Columns_3_ & Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_5_.Q
# Columns_3_ & Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_4_.Q ; (2 pterms, 6 signals)
Chip1_current_state_3_.C = OSC_CLK_in ; (1 pterm, 1 signal)
Chip1_current_state_3_.AR = CD ; (1 pterm, 1 signal)
Chip1_current_state_4_.D = !( Columns_3_ & Columns_2_ & Columns_1_
& Columns_0_
# !Chip1_current_state_5_.Q & !Chip1_current_state_4_.Q ) ; (2 pterms, 6 signals)
Chip1_current_state_4_.C = OSC_CLK_in ; (1 pterm, 1 signal)
Chip1_current_state_4_.AR = CD ; (1 pterm, 1 signal)
Chip1_current_state_5_.D = Columns_3_ & Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_7_.Q
# Columns_3_ & Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_6_.Q ; (2 pterms, 6 signals)
Chip1_current_state_5_.C = OSC_CLK_in ; (1 pterm, 1 signal)
Chip1_current_state_5_.AR = CD ; (1 pterm, 1 signal)
Chip1_current_state_6_.D = !( Columns_3_ & Columns_2_ & Columns_1_
& Columns_0_
# !Chip1_current_state_7_.Q & !Chip1_current_state_6_.Q ) ; (2 pterms, 6 signals)
Chip1_current_state_6_.C = OSC_CLK_in ; (1 pterm, 1 signal)
Chip1_current_state_6_.AR = CD ; (1 pterm, 1 signal)
Chip1_current_state_7_.D = Columns_3_ & Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_1_.Q
# Columns_3_ & Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_0_.Q ; (2 pterms, 6 signals)
Chip1_current_state_7_.C = OSC_CLK_in ; (1 pterm, 1 signal)
Chip1_current_state_7_.AP = CD ; (1 pterm, 1 signal)
D_LEDs_0_ = !Columns_3_ & Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_0_.Q
# Columns_3_ & !Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_4_.Q
# !chip1_data_1_0_0__n ; (3 pterms, 7 signals)
D_LEDs_1_ = !Columns_3_ & Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_2_.Q
# Columns_3_ & !Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_6_.Q
# Columns_3_ & Columns_2_ & !Columns_1_ & Columns_0_
& Chip1_current_state_4_.Q
# Columns_3_ & Columns_2_ & !Columns_1_ & Columns_0_
& Chip1_current_state_6_.Q
# !chip1_n_98_0_n ; (5 pterms, 8 signals)
D_LEDs_2_ = Columns_3_ & !Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_4_.Q
# !chip1_n_141_i_n ; (2 pterms, 6 signals)
D_LEDs_3_ = Columns_3_ & Columns_2_ & Columns_1_ & !Columns_0_
& Chip1_current_state_0_.Q
# Columns_3_ & Columns_2_ & !Columns_1_ & Columns_0_
& Chip1_current_state_2_.Q
# Columns_3_ & !Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_2_.Q
# Columns_3_ & Columns_2_ & Columns_1_ & !Columns_0_
& Chip1_current_state_2_.Q
# !chip1_n_98_0_n ; (5 pterms, 7 signals)
GS = !( !Chip1_current_state_6_.Q & !Chip1_current_state_4_.Q
& !Chip1_current_state_2_.Q & !Chip1_current_state_0_.Q ) ; (1 pterm, 4 signals)
R_LEDs_0_ = !Chip1_current_state_1_.Q & !Chip1_current_state_0_.Q ; (1 pterm, 2 signals)
R_LEDs_1_ = !Chip1_current_state_3_.Q & !Chip1_current_state_2_.Q ; (1 pterm, 2 signals)
R_LEDs_2_ = !Chip1_current_state_5_.Q & !Chip1_current_state_4_.Q ; (1 pterm, 2 signals)
R_LEDs_3_ = !Chip1_current_state_7_.Q & !Chip1_current_state_6_.Q ; (1 pterm, 2 signals)
Rows_0_ = !Chip1_current_state_1_.Q & !Chip1_current_state_0_.Q ; (1 pterm, 2 signals)
Rows_1_ = !Chip1_current_state_3_.Q & !Chip1_current_state_2_.Q ; (1 pterm, 2 signals)
Rows_2_ = !Chip1_current_state_5_.Q & !Chip1_current_state_4_.Q ; (1 pterm, 2 signals)
Rows_3_ = !Chip1_current_state_7_.Q & !Chip1_current_state_6_.Q ; (1 pterm, 2 signals)
chip1_data_1_0_0__n = !( Columns_3_ & Columns_2_ & Columns_1_ & !Columns_0_
& Chip1_current_state_0_.Q
# Columns_3_ & Columns_2_ & Columns_1_ & !Columns_0_
& Chip1_current_state_4_.Q
# Chip1_current_state_2_.Q & chip1_n_133_n
# Chip1_current_state_6_.Q & chip1_n_133_n ) ; (4 pterms, 9 signals)
chip1_n_133_n = Columns_3_ & Columns_2_ & !Columns_1_ & Columns_0_
# !Columns_3_ & Columns_2_ & Columns_1_ & Columns_0_ ; (2 pterms, 4 signals)
chip1_n_141_i_n = !( Columns_3_ & Columns_2_ & Columns_1_ & !Columns_0_
& Chip1_current_state_0_.Q
# !Columns_3_ & Columns_2_ & Columns_1_ & Columns_0_
& Chip1_current_state_2_.Q
# Columns_3_ & Columns_2_ & Columns_1_ & !Columns_0_
& Chip1_current_state_2_.Q
# Chip1_current_state_4_.Q & chip1_n_133_n
# Chip1_current_state_0_.Q & chip1_n_133_n ) ; (5 pterms, 8 signals)
chip1_n_98_0_n = !( Columns_3_ & Columns_2_ & Columns_1_ & !Columns_0_
& Chip1_current_state_4_.Q
# Columns_3_ & Columns_2_ & Columns_1_ & !Columns_0_
& Chip1_current_state_6_.Q
# Chip1_current_state_0_.Q & chip1_n_133_n ) ; (3 pterms, 8 signals)
segments_0_ = !( Columns_3_ & Columns_2_ & Columns_1_ & !Columns_0_
& !D_LEDs_1_ & !D_LEDs_0_ & Chip1_current_state_0_.Q & !chip1_n_141_i_n
# Columns_3_ & Columns_2_ & Columns_1_ & !Columns_0_ & !D_LEDs_1_
& !D_LEDs_0_ & Chip1_current_state_2_.Q & !chip1_n_141_i_n
# !D_LEDs_3_ & D_LEDs_2_ & D_LEDs_1_ & D_LEDs_0_
# !D_LEDs_3_ & !D_LEDs_2_ & !D_LEDs_1_
# !D_LEDs_1_ & !D_LEDs_0_ & !chip1_n_98_0_n & !chip1_n_141_i_n ) ; (5 pterms, 12 signals)
segments_1_ = !Columns_3_ & !D_LEDs_0_ & !Chip1_current_state_2_.Q
# !Columns_2_ & !D_LEDs_0_ & !Chip1_current_state_6_.Q
# Columns_3_ & Columns_2_ & !Columns_1_ & Columns_0_ & !D_LEDs_2_
& Chip1_current_state_2_.Q
# Columns_3_ & !Columns_2_ & Columns_1_ & Columns_0_ & !D_LEDs_2_
& Chip1_current_state_2_.Q
# !D_LEDs_3_ & D_LEDs_2_ & !D_LEDs_1_
# D_LEDs_3_ & D_LEDs_1_
# !Columns_3_ & !Columns_2_ & !D_LEDs_0_
# Columns_3_ & Columns_2_ & !D_LEDs_0_
# !Columns_0_ & !D_LEDs_0_
# !Columns_1_ & !D_LEDs_0_ ; (10 pterms, 10 signals)
segments_2_ = !( !D_LEDs_3_ & D_LEDs_2_ & !D_LEDs_1_
# !D_LEDs_2_ & !D_LEDs_1_ & D_LEDs_0_
# !D_LEDs_3_ & D_LEDs_0_ ) ; (3 pterms, 4 signals)
segments_3_ = !( !Columns_3_ & Columns_1_ & !D_LEDs_0_ & !chip1_n_141_i_n
# D_LEDs_3_ & !D_LEDs_2_ & D_LEDs_1_ & chip1_data_1_0_0__n
# D_LEDs_2_ & D_LEDs_1_ & D_LEDs_0_
# !D_LEDs_2_ & !D_LEDs_1_ & D_LEDs_0_ ) ; (4 pterms, 8 signals)
segments_4_ = !( !Columns_3_ & !D_LEDs_3_ & Columns_2_ & Columns_1_
& Columns_0_ & !D_LEDs_2_ & Chip1_current_state_2_.Q
# Columns_3_ & !D_LEDs_3_ & !Columns_2_ & Columns_1_ & Columns_0_
& !D_LEDs_2_ & Chip1_current_state_6_.Q
# D_LEDs_3_ & D_LEDs_2_ & D_LEDs_1_
# D_LEDs_3_ & !D_LEDs_0_ & !chip1_n_141_i_n ) ; (4 pterms, 11 signals)
segments_5_ = !( !D_LEDs_3_ & D_LEDs_2_ & !D_LEDs_1_ & D_LEDs_0_
# D_LEDs_3_ & D_LEDs_1_ & D_LEDs_0_
# !Columns_1_ & !D_LEDs_0_ & !chip1_n_141_i_n
# Columns_3_ & !D_LEDs_0_ & !chip1_n_141_i_n ) ; (4 pterms, 7 signals)
segments_6_ = !( !Columns_3_ & Columns_1_ & !D_LEDs_0_ & !chip1_n_141_i_n
# D_LEDs_3_ & !D_LEDs_2_ & D_LEDs_1_ & D_LEDs_0_
# D_LEDs_3_ & D_LEDs_2_ & !D_LEDs_1_ & D_LEDs_0_
# !D_LEDs_3_ & !D_LEDs_2_ & !D_LEDs_1_ & D_LEDs_0_ ) ; (4 pterms, 7 signals)