#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 #install: C:\ispLEVER_Classic2_0\synpbase #OS: Windows 7 6.2 #Hostname: RAVADADESKTOP #Implementation: counter_bcd_1digit_spld $ Start of Compile #Thu Nov 01 21:56:52 2018 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 @N: : | Running in 64-bit mode Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : counter_bcd_1digit.vhd(18) | Top entity is set to counter_BCD_1digit. VHDL syntax check successful! @N:CD630 : counter_bcd_1digit.vhd(18) | Synthesizing work.counter_bcd_1digit.fsm_like @W:CD721 : counter_bcd_1digit.vhd(39) | syn_enum_encoding should be used on types. Please change syn_encoding to syn_enum_encoding @N:CD233 : counter_bcd_1digit.vhd(34) | Using sequential encoding for type state_type Post processing for work.counter_bcd_1digit.fsm_like @N:CL201 : counter_bcd_1digit.vhd(61) | Trying to extract state machine for register present_state Extracted state machine for register present_state State machine has 10 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 @END At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Nov 01 21:56:52 2018 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 67MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Nov 01 21:56:54 2018 ###########################################################] Map & Optimize Report Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2014.03LC @N:MF248 : | Running in 64-bit mode. Encoding state machine present_state[0:9] (view:work.counter_BCD_1digit(fsm_like)) original code -> new code 0000 -> 0000 0001 -> 0001 0010 -> 0010 0011 -> 0011 0100 -> 0100 0101 -> 0101 0110 -> 0110 0111 -> 0111 1000 -> 1000 1001 -> 1001 --------------------------------------- Resource Usage Report Simple gate primitives: DFFRH 4 uses IBUF 3 uses OBUF 5 uses INV 17 uses AND2 19 uses OR2 3 uses XOR2 1 use @N:FC100 : | Timing Report not generated for this device, please use place and route tools for timing analysis. I-2014.03LC Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 38MB peak: 102MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Nov 01 21:56:55 2018 ###########################################################]