upc eetac_1


Project P7 on standard sequential circuits: counters, data and shift registers


Counter modulo 24 with BCD outputs

1. Specifications

Counter modulo 24 (hour_counter) based on chaining Counter_mod16 blocks (plan C2). The user can select 2 output codes: AM/PM when M = 1, and 00-23 when M = 0.

Icon timing diagram

Fig 1. Symbol of the Hour_Counter and the way it is applied for counting hours in a real-time clock. Example of a timing diagram when M = 0.

System specifications: the Problem 7.6 in the collection.


Learning materials:

- Concept map for designing sequential circuits (pdf), (Visio)

- Tutorial design of a 1-digit BCD synchronous counter (small number of states) like a FSM in P6 (the plan X).

- Design of a binary synchronous counter of a large number of states like a FSM (arithmetic operations the plan Y). The universal binary counter modulo 16 Counter_mod16.

- Designing a binary counter modulo 12 (Counter_mod12) using three different plans to observe the particularities of each one (plan X, plan Y and plan C2)

- Design of a synchronous data register (plan Y or plan C2)

- Design of a synchronous universal shift register  (plan Y or plan C2)


2. Planning

These are some notes and the full discussion.  And this is the project location:


<local drive>/CSD/P7/Hour_counter/files  


It is a lot better if you try to analyse the sequence of tutorials so that you get enough experience to tackle this Hour_counter project.  It is going to be a plan C2 idea: a large counter infered connecting small units (or bricks) such as the Counter_mod16.

Start an EDA synthesis project and inspect the RTL and technology views. Comment them and check the number of DFF used.

Run a functional simulation and a gate level simulation to measure the maximum speed of the counter deduced from the propagation time from CLK to output (tCO). 


3. Development

This is the complete example in VHDL of the Hour_Counter, so you can run and analyse it.  



4. Testing  (does the machine that we have invented work as expected?)

Start the test bench template and add the CLK and inputs activity translating the timing diagram. Make all the timing relative to the CLK_Period constant. 

This picture below shows how a functional simulation of the Hour_counter module can be performed. In this case representing the waveforms for M = '1' when the circuit works in AM-PM mode. 

Hour_counter functional test
Fig 2. Hour_counter waveforms for M = '1'.  



5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources . 


6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.


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