upc eetac_1

Project P7 on dedicated processors

Advanced digital systems with data-path and control unit (FSM)

Programmable timer

1. Specifications

Design a programmable timer using the strategy of a dedicated processor containing datapath circuits to perform de timing operations and the control unit (a finite state machine) to sequence the process.


Fig 1. Symbol of the programmable timer and the sketch on how it has to work.  (Visio). The number T is T1 or T2 or T3 or T4 depending on the Sel_time input. Therefore, counting time means counting pulses or TTCLK periods (the time base) which have a vey well known and stable frequency. Generally, this TCLK signal is derived from a quartz crystal oscillator and is of a different frequency from CLK, which is the system CLK that runs the machine and it's the fastest signal.


System specifications:

- Teamwork, project and time management.

- 8-bit data to program the timing period. 

- Four programmable timing periods: T1, T2, T3 and T4.

- Trigger signal to start the timing period. Non-retriggerable device.

- Timer_out signal goes high while timing.

- Timer_flag signal goes high to indicate the end of the timing period, thus allowing expandability connecting this signal to the Trigger input of the next device.

- Dedicated processor design strategy.


Learning materials:

- Design of a binary synchronous counter of a small number of states. Unit 2.3

- Design of a binary synchronous counter of a large number of states (arithmetic operations). [Reorganising the former Unit 2.5, here in this guided problem there is a similar device, and here you are the Proteus simulation of an universal synchronous counter].

- Design of a synchronous data register (FSM strategy). [Reorganising the former Unit 2.7, in this guided problem there is a similar device].

- Design of a synchronous  universal shift register (FSM strategy). [Reorganising the former Unit 2.10].


2. Planning (Devising a strategy to solve the problem. This is the engineer's job)

Organise the solution of the programmable_timer_8bit.vhd supposing the hierarchical architecture discussed in class. 

These are the initial ideas and in Fig. 2 there is the general architecture of a dedicated processor that we'll adapt to this problem. External inputs and status signals from the datapath establish the next state to go.


Fig. 2. General architecture of a dedicated processor where the control unit or controller is a FSM that handles the circuits in the datapath which are in charge of processing information.

 1) Draw the state diagram of the Timer_FSM.vhd and infer the number of registers required in this project.

2) Solve the Timer_FSM.vhd component:

1) Particularise the general FSM topology to this problem. To which block (CC1, CC2, state register) is connected every input and output?. Which is the number of bits  r required for coding the current and next state signals [r = number of states if one-hot; r = (1/log 2)·log (number of states) if binary or Gray]?

2) Deduce the truth table of the CC1 and CC2 and their corresponding flow charts.

3) Write the VHDL code of the finite state machine adapting an example from our web. Project folder location and file names:


2) Develop the Octuple_MUX4.vhd required to select the time period.

 3) Develop the 8-bit down counter with parallel input. Counter_8bit.vhd

4) Develop the data registers. Data_register_8bit.vhd

5) Optional component: Exact timing using an arithmetic circuit to offset the FSM overhead bits. (the adder or substractor from P4). 

6) Connect all the components (Counter_8bit.vhd, Octuple_MUX4.vhd, Adder_8bit.vhd, Data_register_8bit.vhd) together in the top Programmable_timer.vhd, file and implement and test the system using the Programmable_timer.vht.


3. Development

Here there are the seed files to start this project. You have the complete top schematic files, but some components with their empty architectures yet to be designed (Chip1 in Fig. 3 and Chip8 in Fig. 4). Thus, the point is that all the files included in the project can now be compiled together and so the EDA tool generates the top level schematic as represented in Fig 3, which is the translation into VHDL of the circuit represented in the whiteboard and discussed in class. 

dedicated processor
  Fig. 3. The top RTL view where all the components are connected . NOTE, in the synthesiser shows you this error, don't worry, and go the same to print the RTL view. This is simply because some components are not finished. 

datapath organisation
Fig. 4. The internal datapath structure.
Fig. 5. The timer FSM that controls the sequence of operations to be solved by the datapath. 

Write the code of the Octuple_MUX4.vhd adapting a file from our web or previous problems.

Write the code of the Counter_8bit.vhd adapting a file from the tutorials.

Write the code of the Data_register_8bit.vhd adapting a file from the tutorials.

Write the VHDL file corresponding to the Timer_FSM.vhd  having translated the flow charts of the CC1 and CC2 and copied the state register which is the same always.  

A) State register. We'll use always the same VHDL code description.

B) CC2. Truth table and flow chart if a behavioural description is used, which is normally the best idea because Boolean algebra is left to the EDA synthesiser. The CC2 is required to calculate the outputs at each state.

C) CC1. Truth table and flow chart if a behavioural description is used, which is normally the best idea because Boolean algebra is left to the synthesiser. CC1 is required to calculate the next state to go after the CLK's rising edge.

Run the EDA tool to synthesise the circuit and print and comment the RTL schematic. Check the number of registers (DFF) used in the target chip and justify the value.  Does it match with your initial value?


4. Testing  (does the machine that we have invented work as expected?)

Start the test bench template and add the CLK and inputs activity translating the timing diagram. Make all the timing relative to the CLK_Period constant. 

Complete the template test bench file named Programmable_timer.vht  translating a timing diagram like the one represented above in the specifications into CLK and input signals stimulus processes.

Functional simulation. Run the EDA VHDL tool and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms. Your system may works like the timing diagram discussed in class.

Run the gate-level simulation of the project and measure the maximum frequency of operation. It is worth to know exactly which is the maxim CLK frequency for a given target CPLD or FPGA chip.


5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources . 

This time, better if you organise your own grading/checklist like we did in previous projects. For instance:

- 4p - General project Programmable_Timer discussion 

- 6p - Designing your assigned component.


Remember that in class you'll be required to explain any section of your project individually or in group.


6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.


Other similar projects on sequential circuits

- A summary of projects proposed in the P7 to study several types of synchronous counters.


Other materials of interest