********** Mapped Logic ********** |
FDCPE_CE: FDCPE port map (CE,LDW,CLK,CD,'0','1'); |
FDCPE_Chip1/present_state_FSM_FFd6: FDCPE port map (Chip1/present_state_FSM_FFd6,Chip1/present_state_FSM_FFd6_D,CLK,'0',CD,'1');
Chip1/present_state_FSM_FFd6_D <= ((NOT ST AND Chip1/present_state_FSM_FFd6) OR (NOT ST AND EOP)); |
FDCPE_Chip2/Chip1/present_state1: FDCPE port map (Chip2/Chip1/present_state(1),Chip2/Chip1/present_state_D(1),CLK,CD,'0','1');
Chip2/Chip1/present_state_D(1) <= NOT (((LDA(1) AND NOT A(1)) OR (CE AND NOT LDA(1) AND NOT Chip2/Chip1/present_state(2)) OR (NOT CE AND NOT LDA(1) AND NOT Chip2/Chip1/present_state(1)))); |
FDCPE_Chip2/Chip1/present_state2: FDCPE port map (Chip2/Chip1/present_state(2),Chip2/Chip1/present_state_D(2),CLK,CD,'0','1');
Chip2/Chip1/present_state_D(2) <= NOT (((LDA(1) AND NOT A(2)) OR (CE AND NOT LDA(1) AND NOT Chip2/Chip1/present_state(3)) OR (NOT CE AND NOT LDA(1) AND NOT Chip2/Chip1/present_state(2)))); |
FDCPE_Chip2/Chip1/present_state3: FDCPE port map (Chip2/Chip1/present_state(3),Chip2/Chip1/present_state_D(3),CLK,CD,'0','1');
Chip2/Chip1/present_state_D(3) <= ((LDA(1) AND A(3)) OR (NOT CE AND NOT LDA(1) AND Chip2/Chip1/present_state(3))); |
FDCPE_Chip2/Chip2/present_state1: FDCPE port map (Chip2/Chip2/present_state(1),Chip2/Chip2/present_state_D(1),CLK,CD,'0','1');
Chip2/Chip2/present_state_D(1) <= NOT (((LDA(1) AND NOT B(1)) OR (CE AND NOT LDA(1) AND NOT Chip2/Chip2/present_state(2)) OR (NOT CE AND NOT LDA(1) AND NOT Chip2/Chip2/present_state(1)))); |
FDCPE_Chip2/Chip2/present_state2: FDCPE port map (Chip2/Chip2/present_state(2),Chip2/Chip2/present_state_D(2),CLK,CD,'0','1');
Chip2/Chip2/present_state_D(2) <= NOT (((LDA(1) AND NOT B(2)) OR (CE AND NOT LDA(1) AND NOT Chip2/Chip2/present_state(3)) OR (NOT CE AND NOT LDA(1) AND NOT Chip2/Chip2/present_state(2)))); |
FDCPE_Chip2/Chip2/present_state3: FDCPE port map (Chip2/Chip2/present_state(3),Chip2/Chip2/present_state_D(3),CLK,CD,'0','1');
Chip2/Chip2/present_state_D(3) <= ((LDA(1) AND B(3)) OR (NOT CE AND NOT LDA(1) AND Chip2/Chip2/present_state(3))); |
FDCPE_Chip2/Chip9/present_state0: FDCPE port map (Chip2/Chip9/present_state(0),Chip2/Chip9/present_state_D(0),CLK,CD,'0','1');
Chip2/Chip9/present_state_D(0) <= ((Chip2/Chip9/present_state(0) AND NOT CE) OR (NOT Chip2/Chip9/present_state(0) AND NOT Chip2/Chip9/present_state(2) AND CE)); |
FTCPE_Chip2/Chip9/present_state1: FTCPE port map (Chip2/Chip9/present_state(1),Chip2/Chip9/present_state_T(1),CLK,CD,'0','1');
Chip2/Chip9/present_state_T(1) <= ((Chip2/Chip9/present_state(0) AND NOT Chip2/Chip9/present_state(2) AND CE) OR (Chip2/Chip9/present_state(2) AND CE AND Chip2/Chip9/present_state(1))); |
FDCPE_Chip2/Chip9/present_state2: FDCPE port map (Chip2/Chip9/present_state(2),Chip2/Chip9/present_state_D(2),CLK,CD,'0','1');
Chip2/Chip9/present_state_D(2) <= (Chip2/Chip9/present_state(2) AND NOT CE); |
FDCPE_Chip2/QA0: FDCPE port map (Chip2/QA(0),Chip2/QA_D(0),CLK,CD,'0','1');
Chip2/QA_D(0) <= NOT (((LDA(1) AND NOT A(0)) OR (CE AND NOT LDA(1) AND NOT Chip2/Chip1/present_state(1)) OR (NOT CE AND NOT LDA(1) AND NOT Chip2/QA(0)))); |
FDCPE_Chip2/QB0: FDCPE port map (Chip2/QB(0),Chip2/QB_D(0),CLK,CD,'0','1');
Chip2/QB_D(0) <= NOT (((LDA(1) AND NOT B(0)) OR (CE AND NOT LDA(1) AND NOT Chip2/Chip2/present_state(1)) OR (NOT CE AND NOT LDA(1) AND NOT Chip2/QB(0)))); |
FTCPE_Chip2/QC0: FTCPE port map (Chip2/QC(0),Chip2/QC_T(0),CLK,CD,'0','1');
Chip2/QC_T(0) <= ((LDW AND Chip2/QC(0) AND NOT Chip2/QB(0) AND NOT Chip2/QA(0)) OR (LDW AND NOT Chip2/QC(0) AND Chip2/QB(0) AND Chip2/QA(0))); |
FDCPE_Chip2/QW0: FDCPE port map (Chip2/QW(0),Chip2/QW_D(0),CLK,CD,'0','1');
Chip2/QW_D(0) <= NOT (((LDW AND NOT Chip2/QW(1)) OR (NOT LDW AND NOT Chip2/QW(0)))); |
FDCPE_Chip2/QW1: FDCPE port map (Chip2/QW(1),Chip2/QW_D(1),CLK,CD,'0','1');
Chip2/QW_D(1) <= NOT (((LDW AND NOT Chip2/QW(2)) OR (NOT LDW AND NOT Chip2/QW(1)))); |
FDCPE_Chip2/QW2: FDCPE port map (Chip2/QW(2),Chip2/QW_D(2),CLK,CD,'0','1');
Chip2/QW_D(2) <= NOT (((LDW AND NOT Chip2/QW(3)) OR (NOT LDW AND NOT Chip2/QW(2)))); |
FDCPE_Chip2/QW3: FDCPE port map (Chip2/QW(3),Chip2/QW_D(3),CLK,CD,'0','1');
Chip2/QW_D(3) <= NOT ((LDW AND Chip2/QB(0)) XOR ((NOT LDW AND NOT Chip2/QW(3)) OR (LDW AND Chip2/QC(0) AND Chip2/QA(0)) OR (LDW AND NOT Chip2/QC(0) AND NOT Chip2/QA(0)))); |
FDCPE_Cout: FDCPE port map (Cout,Cout_D,CLK,CD,'0','1');
Cout_D <= NOT (((NOT Cout AND NOT LDS) OR (LDS AND NOT Chip2/QC(0)))); |
FDCPE_EOP: FDCPE port map (EOP,EOP_D,CLK,CD,'0','1');
EOP_D <= NOT (((NOT LDS AND NOT ST) OR (NOT LDS AND NOT EOP))); |
FDCPE_LDA1: FDCPE port map (LDA(1),LDA_D(1),CLK,CD,'0','1');
LDA_D(1) <= (ST AND Chip1/present_state_FSM_FFd6); |
FDCPE_LDS: FDCPE port map (LDS,LDS_D,CLK,CD,'0','1');
LDS_D <= (Chip2/Chip9/present_state(0) AND NOT Chip2/Chip9/present_state(2) AND CE AND Chip2/Chip9/present_state(1)); |
FDCPE_LDW: FDCPE port map (LDW,LDW_D,CLK,CD,'0','1');
LDW_D <= NOT (((NOT CE AND NOT LDA(1)) OR (Chip2/Chip9/present_state(0) AND NOT Chip2/Chip9/present_state(2) AND CE AND Chip2/Chip9/present_state(1) AND NOT LDA(1)))); |
FDCPE_S0: FDCPE port map (S(0),S_D(0),CLK,CD,'0','1');
S_D(0) <= NOT (((LDS AND NOT Chip2/QW(0)) OR (NOT LDS AND NOT S(0)))); |
FDCPE_S1: FDCPE port map (S(1),S_D(1),CLK,CD,'0','1');
S_D(1) <= NOT (((LDS AND NOT Chip2/QW(1)) OR (NOT LDS AND NOT S(1)))); |
FDCPE_S2: FDCPE port map (S(2),S_D(2),CLK,CD,'0','1');
S_D(2) <= NOT (((LDS AND NOT Chip2/QW(2)) OR (NOT LDS AND NOT S(2)))); |
FDCPE_S3: FDCPE port map (S(3),S_D(3),CLK,CD,'0','1');
S_D(3) <= NOT (((LDS AND NOT Chip2/QW(3)) OR (NOT LDS AND NOT S(3)))); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |