Timing Report

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Design Name Adder_4bit_serial
Device, Speed (SpeedFile Version) XC2C256, -7 (14.0 Advance Product Specification)
Date Created Fri Nov 29 14:12:08 2013
Created By Timing Report Generator: version P.68d
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 7.100 ns.
Max. Clock Frequency (fSYSTEM) 140.845 MHz.
Limited by Cycle Time for CLK
Clock to Setup (tCYC) 7.100 ns.
Setup to Clock at the Pad (tSU) 3.300 ns.
Clock Pad to Output Pad Delay (tCO) 6.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 7.1 87 87
AUTO_TS_P2P 0.0 6.0 6 6
AUTO_TS_P2F 0.0 6.0 12 12
AUTO_TS_F2P 0.0 3.3 6 6


Constraint: TS1000

Description: PERIOD:PERIOD_CLK:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CE.Q to Chip2/Chip1/present_state<1>.D 0.000 7.100 -7.100
CE.Q to Chip2/Chip1/present_state<2>.D 0.000 7.100 -7.100
CE.Q to Chip2/Chip1/present_state<3>.D 0.000 7.100 -7.100


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK to Cout 0.000 6.000 -6.000
CLK to EOP 0.000 6.000 -6.000
CLK to S<0> 0.000 6.000 -6.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
A<0> to Chip2/QA<0>.D 0.000 6.000 -6.000
A<1> to Chip2/Chip1/present_state<1>.D 0.000 6.000 -6.000
A<2> to Chip2/Chip1/present_state<2>.D 0.000 6.000 -6.000


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Cout.Q to Cout 0.000 3.300 -3.300
EOP.Q to EOP 0.000 3.300 -3.300
S<0>.Q to S<0> 0.000 3.300 -3.300



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK 140.845 Limited by Cycle Time for CLK

Setup/Hold Times for Clocks

Setup/Hold Times for Clock CLK
Source Pad Setup to clk (edge) Hold to clk (edge)
A<0> 3.300 0.000
A<1> 3.300 0.000
A<2> 3.300 0.000
A<3> 3.300 0.000
B<0> 3.300 0.000
B<1> 3.300 0.000
B<2> 3.300 0.000
B<3> 3.300 0.000
ST 3.300 0.000


Clock to Pad Timing

Clock CLK to Pad
Destination Pad Clock (edge) to Pad
Cout 6.000
EOP 6.000
S<0> 6.000
S<1> 6.000
S<2> 6.000
S<3> 6.000


Clock to Setup Times for Clocks

Clock to Setup for clock CLK
Source Destination Delay
CE.Q Chip2/Chip1/present_state<1>.D 7.100
CE.Q Chip2/Chip1/present_state<2>.D 7.100
CE.Q Chip2/Chip1/present_state<3>.D 7.100
CE.Q Chip2/Chip2/present_state<1>.D 7.100
CE.Q Chip2/Chip2/present_state<2>.D 7.100
CE.Q Chip2/Chip2/present_state<3>.D 7.100
CE.Q Chip2/Chip9/present_state<0>.D 7.100
CE.Q Chip2/Chip9/present_state<1>.D 7.100
CE.Q Chip2/QA<0>.D 7.100
CE.Q Chip2/QB<0>.D 7.100
CE.Q LDW.D 7.100
Chip1/present_state_FSM_FFd6.Q Chip1/present_state_FSM_FFd6.D 7.100
Chip2/Chip1/present_state<1>.Q Chip2/Chip1/present_state<1>.D 7.100
Chip2/Chip1/present_state<1>.Q Chip2/QA<0>.D 7.100
Chip2/Chip1/present_state<2>.Q Chip2/Chip1/present_state<1>.D 7.100
Chip2/Chip1/present_state<2>.Q Chip2/Chip1/present_state<2>.D 7.100
Chip2/Chip1/present_state<3>.Q Chip2/Chip1/present_state<2>.D 7.100
Chip2/Chip1/present_state<3>.Q Chip2/Chip1/present_state<3>.D 7.100
Chip2/Chip2/present_state<1>.Q Chip2/Chip2/present_state<1>.D 7.100
Chip2/Chip2/present_state<1>.Q Chip2/QB<0>.D 7.100
Chip2/Chip2/present_state<2>.Q Chip2/Chip2/present_state<1>.D 7.100
Chip2/Chip2/present_state<2>.Q Chip2/Chip2/present_state<2>.D 7.100
Chip2/Chip2/present_state<3>.Q Chip2/Chip2/present_state<2>.D 7.100
Chip2/Chip2/present_state<3>.Q Chip2/Chip2/present_state<3>.D 7.100
Chip2/Chip9/present_state<0>.Q Chip2/Chip9/present_state<0>.D 7.100
Chip2/Chip9/present_state<0>.Q Chip2/Chip9/present_state<1>.D 7.100
Chip2/Chip9/present_state<0>.Q LDW.D 7.100
Chip2/Chip9/present_state<1>.Q Chip2/Chip9/present_state<1>.D 7.100
Chip2/Chip9/present_state<1>.Q LDW.D 7.100
Chip2/Chip9/present_state<2>.Q Chip2/Chip9/present_state<0>.D 7.100
Chip2/Chip9/present_state<2>.Q Chip2/Chip9/present_state<1>.D 7.100
Chip2/Chip9/present_state<2>.Q LDW.D 7.100
Chip2/QA<0>.Q Chip2/QA<0>.D 7.100
Chip2/QA<0>.Q Chip2/QC<0>.D 7.100
Chip2/QA<0>.Q Chip2/QW<3>.D 7.100
Chip2/QB<0>.Q Chip2/QB<0>.D 7.100
Chip2/QB<0>.Q Chip2/QC<0>.D 7.100
Chip2/QC<0>.Q Chip2/QC<0>.D 7.100
Chip2/QC<0>.Q Chip2/QW<3>.D 7.100
Chip2/QC<0>.Q Cout.D 7.100
Chip2/QW<0>.Q Chip2/QW<0>.D 7.100
Chip2/QW<0>.Q S<0>.D 7.100
Chip2/QW<1>.Q Chip2/QW<0>.D 7.100
Chip2/QW<1>.Q Chip2/QW<1>.D 7.100
Chip2/QW<1>.Q S<1>.D 7.100
Chip2/QW<2>.Q Chip2/QW<1>.D 7.100
Chip2/QW<2>.Q Chip2/QW<2>.D 7.100
Chip2/QW<2>.Q S<2>.D 7.100
Chip2/QW<3>.Q Chip2/QW<2>.D 7.100
Chip2/QW<3>.Q Chip2/QW<3>.D 7.100
Chip2/QW<3>.Q S<3>.D 7.100
Cout.Q Cout.D 7.100
EOP.Q Chip1/present_state_FSM_FFd6.D 7.100
EOP.Q EOP.D 7.100
LDA<1>.Q Chip2/Chip1/present_state<1>.D 7.100
LDA<1>.Q Chip2/Chip1/present_state<2>.D 7.100
LDA<1>.Q Chip2/Chip1/present_state<3>.D 7.100
LDA<1>.Q Chip2/Chip2/present_state<1>.D 7.100
LDA<1>.Q Chip2/Chip2/present_state<2>.D 7.100
LDA<1>.Q Chip2/Chip2/present_state<3>.D 7.100
LDA<1>.Q Chip2/QA<0>.D 7.100
LDA<1>.Q Chip2/QB<0>.D 7.100
LDA<1>.Q LDW.D 7.100
LDS.Q Cout.D 7.100
LDS.Q EOP.D 7.100
LDS.Q S<0>.D 7.100
LDS.Q S<1>.D 7.100
LDS.Q S<2>.D 7.100
LDS.Q S<3>.D 7.100
LDW.Q Chip2/QC<0>.D 7.100
LDW.Q Chip2/QW<0>.D 7.100
LDW.Q Chip2/QW<1>.D 7.100
LDW.Q Chip2/QW<2>.D 7.100
LDW.Q Chip2/QW<3>.D 7.100
S<0>.Q S<0>.D 7.100
S<1>.Q S<1>.D 7.100
S<2>.Q S<2>.D 7.100
S<3>.Q S<3>.D 7.100
CE.Q Chip2/Chip9/present_state<2>.D 6.600
CE.Q LDS.D 6.600
Chip1/present_state_FSM_FFd6.Q LDA<1>.D 6.600
Chip2/Chip9/present_state<0>.Q LDS.D 6.600
Chip2/Chip9/present_state<1>.Q LDS.D 6.600
Chip2/Chip9/present_state<2>.Q Chip2/Chip9/present_state<2>.D 6.600
Chip2/Chip9/present_state<2>.Q LDS.D 6.600
Chip2/QB<0>.Q Chip2/QW<3>.D 6.600
LDW.Q CE.D 6.600


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 111
Number of Timing errors: 111
Analysis Completed: Fri Nov 29 14:12:09 2013