Adder_4bit_serial Project Status (11/29/2013 - 14:12:17) | |||
Project File: | Adder_4bit_serial_prj.xise | Parser Errors: | |
Module Name: | Adder_4bit_serial | Implementation State: | Fitted |
Target Device: | xc2c256-7TQ144 |
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No Errors |
Product Version: | ISE 14.6 |
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7 Warnings (7 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | vie 29. nov 14:11:25 2013 | 0 | 7 Warnings (7 new) | 0 | |
Translation Report | Current | vie 29. nov 14:11:36 2013 | 0 | 0 | 0 | |
CPLD Fitter Report (Text) | Current | vie 29. nov 14:11:47 2013 | 0 | 2 Warnings (1 new) | 0 | |
Power Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
Post-Fit Simulation Model Report |