Adder_4bit_serial Project Status (11/29/2013 - 14:12:17)
Project File: Adder_4bit_serial_prj.xise Parser Errors:
Module Name: Adder_4bit_serial Implementation State: Fitted
Target Device: xc2c256-7TQ144
  • Errors:
No Errors
Product Version:ISE 14.6
  • Warnings:
7 Warnings (7 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentvie 29. nov 14:11:25 201307 Warnings (7 new)0
Translation ReportCurrentvie 29. nov 14:11:36 2013000
CPLD Fitter Report (Text)Currentvie 29. nov 14:11:47 201302 Warnings (1 new)0
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 11/29/2013 - 14:12:17