cpldfit: version P.68d Xilinx Inc. Fitter Report Design Name: Adder_4bit_serial Date: 11-29-2013, 2:11PM Device Used: XC2C256-7-TQ144 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 27 /256 ( 11%) 58 /896 ( 6%) 40 /640 ( 6%) 27 /256 ( 11%) 17 /118 ( 14%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO CTC CTR CTS CTE Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot FB1 16/16* 25/40 37/56 5/ 6 0/1 0/1 0/1 0/1 FB2 11/16 15/40 21/56 1/ 8 0/1 0/1 0/1 0/1 FB3 0/16 0/40 0/56 0/ 6 0/1 0/1 0/1 0/1 FB4 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB5 0/16 0/40 0/56 0/ 5 0/1 0/1 0/1 0/1 FB6 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB7 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB8 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB9 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB10 0/16 0/40 0/56 0/ 9 0/1 0/1 0/1 0/1 FB11 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB12 0/16 0/40 0/56 0/ 6 0/1 0/1 0/1 0/1 FB13 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB14 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB15 0/16 0/40 0/56 0/ 7 0/1 0/1 0/1 0/1 FB16 0/16 0/40 0/56 0/ 7 0/1 0/1 0/1 0/1 ----- ------- ------- ----- --- --- --- --- Total 27/256 40/640 58/896 6/118 0/16 0/16 0/16 0/16 CTC - Control Term Clock CTR - Control Term Reset CTS - Control Term Set CTE - Control Term Output Enable * - Resource is exhausted ** Global Control Resources ** GCK GSR GTS DGE Used/Tot Used/Tot Used/Tot Used/Tot 1/3 1/1 0/4 0/1 Signal 'CLK' mapped onto global clock net GCK1. Signal 'CD' mapped onto global set/reset net GSR. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 9 9 | I/O : 11 108 Output : 6 6 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 4 4 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | CDR/IO : 0 1 GSR : 1 1 | DGE/IO : 0 1 ---- ---- Total 17 17 End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'Adder_4bit_serial.ise'. WARNING:Cpld:1058 - Removing unused input(s) 'Cin'. The input(s) are unused after optimization. Please verify functionality via simulation. ************************* Summary of Mapped Logic ************************ ** 6 Outputs ** Signal Total Total Bank Loc Pin Pin Pin I/O I/O Slew Reg Reg Init Name Pts Inps No. Type Use STD Style Rate Use State Cout 2 3 2 FB1_4 142 I/O O LVCMOS18 FAST DFF RESET S<0> 2 3 2 FB1_6 140 I/O O LVCMOS18 FAST DFF RESET S<1> 2 3 2 FB1_12 139 I/O O LVCMOS18 FAST DFF RESET S<2> 2 3 2 FB1_13 138 I/O O LVCMOS18 FAST DFF RESET S<3> 2 3 2 FB1_14 137 I/O O LVCMOS18 FAST DFF RESET EOP 2 3 2 FB2_1 2 GTS/I/O O LVCMOS18 FAST DFF RESET ** 21 Buried Nodes ** Signal Total Total Loc Reg Reg Init Name Pts Inps Use State Chip2/Chip1/present_state<3> 2 4 FB1_1 DFF RESET Chip2/Chip1/present_state<2> 3 5 FB1_2 DFF RESET Chip2/QB<0> 3 5 FB1_3 DFF RESET Chip2/Chip1/present_state<1> 3 5 FB1_5 DFF RESET Chip2/QA<0> 3 5 FB1_7 DFF RESET CE 1 1 FB1_8 DFF RESET Chip2/QC<0> 2 4 FB1_9 TFF RESET Chip2/QW<3> 4 5 FB1_10 DFF RESET Chip2/QW<2> 2 3 FB1_11 DFF RESET Chip2/QW<1> 2 3 FB1_15 DFF RESET Chip2/QW<0> 2 3 FB1_16 DFF RESET Chip2/Chip2/present_state<3> 2 4 FB2_2 DFF RESET LDW 2 5 FB2_6 DFF RESET Chip2/Chip9/present_state<1> 2 4 FB2_7 TFF RESET LDS 1 4 FB2_8 DFF RESET Chip2/Chip9/present_state<0> 2 3 FB2_9 DFF RESET Chip2/Chip9/present_state<2> 1 2 FB2_10 DFF RESET LDA<1> 1 2 FB2_11 DFF RESET Chip2/Chip2/present_state<1> 3 5 FB2_14 DFF RESET Chip2/Chip2/present_state<2> 3 5 FB2_15 DFF RESET Chip1/present_state_FSM_FFd6 2 3 FB2_16 DFF/S SET ** 11 Inputs ** Signal Bank Loc Pin Pin Pin I/O I/O Name No. Type Use STD Style CD 2 FB1_3 143 GSR/I/O GSR LVCMOS18 KPR B<1> 2 FB2_3 3 GTS/I/O I LVCMOS18 KPR B<2> 2 FB2_4 4 I/O I LVCMOS18 KPR B<3> 2 FB2_5 5 GTS/I/O I LVCMOS18 KPR ST 2 FB2_12 6 GTS/I/O I LVCMOS18 KPR A<0> 2 FB2_13 7 I/O I LVCMOS18 KPR A<1> 2 FB2_14 9 I/O I LVCMOS18 KPR A<2> 2 FB2_15 10 I/O I LVCMOS18 KPR A<3> 2 FB3_1 136 I/O I LVCMOS18 KPR B<0> 2 FB3_2 135 I/O I LVCMOS18 KPR CLK 1 FB5_4 32 GCK/I/O GCK LVCMOS18 KPR Legend: Pin No. - ~ - User Assigned I/O Style - OD - OpenDrain - PU - Pullup - KPR - Keeper - S - SchmittTrigger - DG - DataGate Reg Use - LATCH - Transparent latch - DFF - D-flip-flop - DEFF - D-flip-flop with clock enable - TFF - T-flip-flop - TDFF - Dual-edge-triggered T-flip-flop - DDFF - Dual-edge-triggered flip-flop - DDEFF - Dual-edge-triggered flip-flop with clock enable /S (after any above flop/latch type) indicates initial state is Set ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset VRF - Vref Pin No. - ~ - User Assigned *********************************** FB1 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 25/15 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 37/19 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use Chip2/Chip1/present_state<3> 2 FB1_1 (b) (b) Chip2/Chip1/present_state<2> 3 FB1_2 (b) (b) Chip2/QB<0> 3 FB1_3 143 GSR/I/O GSR Cout 2 FB1_4 142 I/O O Chip2/Chip1/present_state<1> 3 FB1_5 (b) (b) S<0> 2 FB1_6 140 I/O O Chip2/QA<0> 3 FB1_7 (b) (b) CE 1 FB1_8 (b) (b) Chip2/QC<0> 2 FB1_9 (b) (b) Chip2/QW<3> 4 FB1_10 (b) (b) Chip2/QW<2> 2 FB1_11 (b) (b) S<1> 2 FB1_12 139 I/O O S<2> 2 FB1_13 138 I/O O S<3> 2 FB1_14 137 I/O O Chip2/QW<1> 2 FB1_15 (b) (b) Chip2/QW<0> 2 FB1_16 (b) (b) Signals Used by Logic in Function Block 1: A<0> 10: Chip2/Chip2/present_state<1> 18: Cout 2: A<1> 11: Chip2/QA<0> 19: LDA<1> 3: A<2> 12: Chip2/QB<0> 20: LDS 4: A<3> 13: Chip2/QC<0> 21: LDW 5: B<0> 14: Chip2/QW<0> 22: S<0> 6: CE 15: Chip2/QW<1> 23: S<1> 7: Chip2/Chip1/present_state<1> 16: Chip2/QW<2> 24: S<2> 8: Chip2/Chip1/present_state<2> 17: Chip2/QW<3> 25: S<3> 9: Chip2/Chip1/present_state<3> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs Chip2/Chip1/present_state<3> ...X.X..X.........X..................... 4 Chip2/Chip1/present_state<2> ..X..X.XX.........X..................... 5 Chip2/QB<0> ....XX...X.X......X..................... 5 Cout ............X....X.X.................... 3 Chip2/Chip1/present_state<1> .X...XXX..........X..................... 5 S<0> .............X.....X.X.................. 3 Chip2/QA<0> X....XX...X.......X..................... 5 CE ....................X................... 1 Chip2/QC<0> ..........XXX.......X................... 4 Chip2/QW<3> ..........XXX...X...X................... 5 Chip2/QW<2> ...............XX...X................... 3 S<1> ..............X....X..X................. 3 S<2> ...............X...X...X................ 3 S<3> ................X..X....X............... 3 Chip2/QW<1> ..............XX....X................... 3 Chip2/QW<0> .............XX.....X................... 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 15/25 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 21/35 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use EOP 2 FB2_1 2 GTS/I/O O Chip2/Chip2/present_state<3> 2 FB2_2 (b) (b) (unused) 0 FB2_3 3 GTS/I/O I (unused) 0 FB2_4 4 I/O I (unused) 0 FB2_5 5 GTS/I/O I LDW 2 FB2_6 (b) (b) Chip2/Chip9/present_state<1> 2 FB2_7 (b) (b) LDS 1 FB2_8 (b) (b) Chip2/Chip9/present_state<0> 2 FB2_9 (b) (b) Chip2/Chip9/present_state<2> 1 FB2_10 (b) (b) LDA<1> 1 FB2_11 (b) (b) (unused) 0 FB2_12 6 GTS/I/O I (unused) 0 FB2_13 7 I/O I Chip2/Chip2/present_state<1> 3 FB2_14 9 I/O I Chip2/Chip2/present_state<2> 3 FB2_15 10 I/O I Chip1/present_state_FSM_FFd6 2 FB2_16 (b) (b) Signals Used by Logic in Function Block 1: B<1> 6: Chip2/Chip2/present_state<1> 11: Chip2/Chip9/present_state<2> 2: B<2> 7: Chip2/Chip2/present_state<2> 12: EOP 3: B<3> 8: Chip2/Chip2/present_state<3> 13: LDA<1> 4: CE 9: Chip2/Chip9/present_state<0> 14: LDS 5: Chip1/present_state_FSM_FFd6 10: Chip2/Chip9/present_state<1> 15: ST Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs EOP ...........X.XX......................... 3 Chip2/Chip2/present_state<3> ..XX...X....X........................... 4 LDW ...X....XXX.X........................... 5 Chip2/Chip9/present_state<1> ...X....XXX............................. 4 LDS ...X....XXX............................. 4 Chip2/Chip9/present_state<0> ...X....X.X............................. 3 Chip2/Chip9/present_state<2> ...X......X............................. 2 LDA<1> ....X.........X......................... 2 Chip2/Chip2/present_state<1> X..X.XX.....X........................... 5 Chip2/Chip2/present_state<2> .X.X..XX....X........................... 5 Chip1/present_state_FSM_FFd6 ....X......X..X......................... 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB3_1 136 I/O I (unused) 0 FB3_2 135 I/O I (unused) 0 FB3_3 134 I/O (unused) 0 FB3_4 (b) (unused) 0 FB3_5 133 I/O (unused) 0 FB3_6 (b) (unused) 0 FB3_7 (b) (unused) 0 FB3_8 (b) (unused) 0 FB3_9 (b) (unused) 0 FB3_10 (b) (unused) 0 FB3_11 (b) (unused) 0 FB3_12 (b) (unused) 0 FB3_13 (b) (unused) 0 FB3_14 132 I/O (unused) 0 FB3_15 (b) (unused) 0 FB3_16 131 I/O *********************************** FB4 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB4_1 11 I/O (unused) 0 FB4_2 12 I/O (unused) 0 FB4_3 13 I/O (unused) 0 FB4_4 14 I/O (unused) 0 FB4_5 15 I/O (unused) 0 FB4_6 16 I/O (unused) 0 FB4_7 (b) (unused) 0 FB4_8 (b) (unused) 0 FB4_9 (b) (unused) 0 FB4_10 (b) (unused) 0 FB4_11 (b) (unused) 0 FB4_12 17 I/O (unused) 0 FB4_13 (b) (unused) 0 FB4_14 18 I/O (unused) 0 FB4_15 (b) (unused) 0 FB4_16 (b) *********************************** FB5 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB5_1 (b) (unused) 0 FB5_2 33 I/O (unused) 0 FB5_3 (b) (unused) 0 FB5_4 32 GCK/I/O GCK (unused) 0 FB5_5 31 I/O (unused) 0 FB5_6 30 GCK/I/O (unused) 0 FB5_7 (b) (unused) 0 FB5_8 (b) (unused) 0 FB5_9 (b) (unused) 0 FB5_10 (b) (unused) 0 FB5_11 (b) (unused) 0 FB5_12 (b) (unused) 0 FB5_13 (b) (unused) 0 FB5_14 28 I/O (unused) 0 FB5_15 (b) (unused) 0 FB5_16 (b) *********************************** FB6 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB6_1 34 I/O (unused) 0 FB6_2 35 CDR/I/O (unused) 0 FB6_3 (b) (unused) 0 FB6_4 38 GCK/I/O (unused) 0 FB6_5 (b) (unused) 0 FB6_6 (b) (unused) 0 FB6_7 (b) (unused) 0 FB6_8 (b) (unused) 0 FB6_9 (b) (unused) 0 FB6_10 (b) (unused) 0 FB6_11 (b) (unused) 0 FB6_12 39 DGE/I/O (unused) 0 FB6_13 40 I/O (unused) 0 FB6_14 41 I/O (unused) 0 FB6_15 42 I/O (unused) 0 FB6_16 43 I/O *********************************** FB7 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB7_1 (b) (unused) 0 FB7_2 (b) (unused) 0 FB7_3 (b) (unused) 0 FB7_4 (b) (unused) 0 FB7_5 26 I/O (unused) 0 FB7_6 25 I/O (unused) 0 FB7_7 (b) (unused) 0 FB7_8 (b) (unused) 0 FB7_9 (b) (unused) 0 FB7_10 (b) (unused) 0 FB7_11 24 I/O (unused) 0 FB7_12 23 I/O (unused) 0 FB7_13 22 I/O (unused) 0 FB7_14 21 I/O (unused) 0 FB7_15 20 I/O (unused) 0 FB7_16 19 I/O *********************************** FB8 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB8_1 44 I/O (unused) 0 FB8_2 45 I/O (unused) 0 FB8_3 46 I/O (unused) 0 FB8_4 (b) (unused) 0 FB8_5 48 I/O (unused) 0 FB8_6 49 I/O (unused) 0 FB8_7 (b) (unused) 0 FB8_8 (b) (unused) 0 FB8_9 (b) (unused) 0 FB8_10 (b) (unused) 0 FB8_11 50 I/O (unused) 0 FB8_12 51 I/O (unused) 0 FB8_13 52 I/O (unused) 0 FB8_14 (b) (unused) 0 FB8_15 (b) (unused) 0 FB8_16 (b) *********************************** FB9 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB9_1 112 I/O (unused) 0 FB9_2 113 I/O (unused) 0 FB9_3 (b) (unused) 0 FB9_4 114 I/O (unused) 0 FB9_5 (b) (unused) 0 FB9_6 115 I/O (unused) 0 FB9_7 (b) (unused) 0 FB9_8 (b) (unused) 0 FB9_9 (b) (unused) 0 FB9_10 (b) (unused) 0 FB9_11 (b) (unused) 0 FB9_12 116 I/O (unused) 0 FB9_13 117 I/O (unused) 0 FB9_14 118 I/O (unused) 0 FB9_15 119 I/O (unused) 0 FB9_16 (b) *********************************** FB10 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB10_1 111 I/O (unused) 0 FB10_2 110 I/O (unused) 0 FB10_3 107 I/O (unused) 0 FB10_4 106 I/O (unused) 0 FB10_5 105 I/O (unused) 0 FB10_6 104 I/O (unused) 0 FB10_7 (b) (unused) 0 FB10_8 (b) (unused) 0 FB10_9 (b) (unused) 0 FB10_10 (b) (unused) 0 FB10_11 (b) (unused) 0 FB10_12 103 I/O (unused) 0 FB10_13 (b) (unused) 0 FB10_14 102 I/O (unused) 0 FB10_15 (b) (unused) 0 FB10_16 101 I/O *********************************** FB11 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB11_1 (b) (unused) 0 FB11_2 (b) (unused) 0 FB11_3 (b) (unused) 0 FB11_4 (b) (unused) 0 FB11_5 120 I/O (unused) 0 FB11_6 121 I/O (unused) 0 FB11_7 (b) (unused) 0 FB11_8 (b) (unused) 0 FB11_9 (b) (unused) 0 FB11_10 (b) (unused) 0 FB11_11 124 I/O (unused) 0 FB11_12 125 I/O (unused) 0 FB11_13 126 I/O (unused) 0 FB11_14 128 I/O (unused) 0 FB11_15 129 I/O (unused) 0 FB11_16 130 I/O *********************************** FB12 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB12_1 (b) (unused) 0 FB12_2 100 I/O (unused) 0 FB12_3 (b) (unused) 0 FB12_4 (b) (unused) 0 FB12_5 (b) (unused) 0 FB12_6 (b) (unused) 0 FB12_7 (b) (unused) 0 FB12_8 (b) (unused) 0 FB12_9 (b) (unused) 0 FB12_10 (b) (unused) 0 FB12_11 98 I/O (unused) 0 FB12_12 97 I/O (unused) 0 FB12_13 96 I/O (unused) 0 FB12_14 95 I/O (unused) 0 FB12_15 94 I/O (unused) 0 FB12_16 (b) *********************************** FB13 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB13_1 75 I/O (unused) 0 FB13_2 76 I/O (unused) 0 FB13_3 77 I/O (unused) 0 FB13_4 (b) (unused) 0 FB13_5 78 I/O (unused) 0 FB13_6 79 I/O (unused) 0 FB13_7 (b) (unused) 0 FB13_8 (b) (unused) 0 FB13_9 (b) (unused) 0 FB13_10 (b) (unused) 0 FB13_11 (b) (unused) 0 FB13_12 80 I/O (unused) 0 FB13_13 81 I/O (unused) 0 FB13_14 82 I/O (unused) 0 FB13_15 (b) (unused) 0 FB13_16 (b) *********************************** FB14 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB14_1 74 I/O (unused) 0 FB14_2 71 I/O (unused) 0 FB14_3 70 I/O (unused) 0 FB14_4 69 I/O (unused) 0 FB14_5 (b) (unused) 0 FB14_6 68 I/O (unused) 0 FB14_7 (b) (unused) 0 FB14_8 (b) (unused) 0 FB14_9 (b) (unused) 0 FB14_10 (b) (unused) 0 FB14_11 (b) (unused) 0 FB14_12 (b) (unused) 0 FB14_13 66 I/O (unused) 0 FB14_14 64 I/O (unused) 0 FB14_15 (b) (unused) 0 FB14_16 61 I/O *********************************** FB15 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB15_1 (b) (unused) 0 FB15_2 83 I/O (unused) 0 FB15_3 (b) (unused) 0 FB15_4 (b) (unused) 0 FB15_5 (b) (unused) 0 FB15_6 (b) (unused) 0 FB15_7 (b) (unused) 0 FB15_8 (b) (unused) 0 FB15_9 (b) (unused) 0 FB15_10 (b) (unused) 0 FB15_11 85 I/O (unused) 0 FB15_12 86 I/O (unused) 0 FB15_13 87 I/O (unused) 0 FB15_14 88 I/O (unused) 0 FB15_15 91 I/O (unused) 0 FB15_16 92 I/O *********************************** FB16 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB16_1 (b) (unused) 0 FB16_2 (b) (unused) 0 FB16_3 (b) (unused) 0 FB16_4 (b) (unused) 0 FB16_5 60 I/O (unused) 0 FB16_6 59 I/O (unused) 0 FB16_7 (b) (unused) 0 FB16_8 (b) (unused) 0 FB16_9 (b) (unused) 0 FB16_10 (b) (unused) 0 FB16_11 58 I/O (unused) 0 FB16_12 57 I/O (unused) 0 FB16_13 56 I/O (unused) 0 FB16_14 (b) (unused) 0 FB16_15 54 I/O (unused) 0 FB16_16 53 I/O ******************************* Equations ******************************** ********** Mapped Logic ********** FDCPE_CE: FDCPE port map (CE,LDW,CLK,CD,'0','1'); FDCPE_Chip1/present_state_FSM_FFd6: FDCPE port map (Chip1/present_state_FSM_FFd6,Chip1/present_state_FSM_FFd6_D,CLK,'0',CD,'1'); Chip1/present_state_FSM_FFd6_D <= ((NOT ST AND Chip1/present_state_FSM_FFd6) OR (NOT ST AND EOP)); FDCPE_Chip2/Chip1/present_state1: FDCPE port map (Chip2/Chip1/present_state(1),Chip2/Chip1/present_state_D(1),CLK,CD,'0','1'); Chip2/Chip1/present_state_D(1) <= NOT (((LDA(1) AND NOT A(1)) OR (CE AND NOT LDA(1) AND NOT Chip2/Chip1/present_state(2)) OR (NOT CE AND NOT LDA(1) AND NOT Chip2/Chip1/present_state(1)))); FDCPE_Chip2/Chip1/present_state2: FDCPE port map (Chip2/Chip1/present_state(2),Chip2/Chip1/present_state_D(2),CLK,CD,'0','1'); Chip2/Chip1/present_state_D(2) <= NOT (((LDA(1) AND NOT A(2)) OR (CE AND NOT LDA(1) AND NOT Chip2/Chip1/present_state(3)) OR (NOT CE AND NOT LDA(1) AND NOT Chip2/Chip1/present_state(2)))); FDCPE_Chip2/Chip1/present_state3: FDCPE port map (Chip2/Chip1/present_state(3),Chip2/Chip1/present_state_D(3),CLK,CD,'0','1'); Chip2/Chip1/present_state_D(3) <= ((LDA(1) AND A(3)) OR (NOT CE AND NOT LDA(1) AND Chip2/Chip1/present_state(3))); FDCPE_Chip2/Chip2/present_state1: FDCPE port map (Chip2/Chip2/present_state(1),Chip2/Chip2/present_state_D(1),CLK,CD,'0','1'); Chip2/Chip2/present_state_D(1) <= NOT (((LDA(1) AND NOT B(1)) OR (CE AND NOT LDA(1) AND NOT Chip2/Chip2/present_state(2)) OR (NOT CE AND NOT LDA(1) AND NOT Chip2/Chip2/present_state(1)))); FDCPE_Chip2/Chip2/present_state2: FDCPE port map (Chip2/Chip2/present_state(2),Chip2/Chip2/present_state_D(2),CLK,CD,'0','1'); Chip2/Chip2/present_state_D(2) <= NOT (((LDA(1) AND NOT B(2)) OR (CE AND NOT LDA(1) AND NOT Chip2/Chip2/present_state(3)) OR (NOT CE AND NOT LDA(1) AND NOT Chip2/Chip2/present_state(2)))); FDCPE_Chip2/Chip2/present_state3: FDCPE port map (Chip2/Chip2/present_state(3),Chip2/Chip2/present_state_D(3),CLK,CD,'0','1'); Chip2/Chip2/present_state_D(3) <= ((LDA(1) AND B(3)) OR (NOT CE AND NOT LDA(1) AND Chip2/Chip2/present_state(3))); FDCPE_Chip2/Chip9/present_state0: FDCPE port map (Chip2/Chip9/present_state(0),Chip2/Chip9/present_state_D(0),CLK,CD,'0','1'); Chip2/Chip9/present_state_D(0) <= ((Chip2/Chip9/present_state(0) AND NOT CE) OR (NOT Chip2/Chip9/present_state(0) AND NOT Chip2/Chip9/present_state(2) AND CE)); FTCPE_Chip2/Chip9/present_state1: FTCPE port map (Chip2/Chip9/present_state(1),Chip2/Chip9/present_state_T(1),CLK,CD,'0','1'); Chip2/Chip9/present_state_T(1) <= ((Chip2/Chip9/present_state(0) AND NOT Chip2/Chip9/present_state(2) AND CE) OR (Chip2/Chip9/present_state(2) AND CE AND Chip2/Chip9/present_state(1))); FDCPE_Chip2/Chip9/present_state2: FDCPE port map (Chip2/Chip9/present_state(2),Chip2/Chip9/present_state_D(2),CLK,CD,'0','1'); Chip2/Chip9/present_state_D(2) <= (Chip2/Chip9/present_state(2) AND NOT CE); FDCPE_Chip2/QA0: FDCPE port map (Chip2/QA(0),Chip2/QA_D(0),CLK,CD,'0','1'); Chip2/QA_D(0) <= NOT (((LDA(1) AND NOT A(0)) OR (CE AND NOT LDA(1) AND NOT Chip2/Chip1/present_state(1)) OR (NOT CE AND NOT LDA(1) AND NOT Chip2/QA(0)))); FDCPE_Chip2/QB0: FDCPE port map (Chip2/QB(0),Chip2/QB_D(0),CLK,CD,'0','1'); Chip2/QB_D(0) <= NOT (((LDA(1) AND NOT B(0)) OR (CE AND NOT LDA(1) AND NOT Chip2/Chip2/present_state(1)) OR (NOT CE AND NOT LDA(1) AND NOT Chip2/QB(0)))); FTCPE_Chip2/QC0: FTCPE port map (Chip2/QC(0),Chip2/QC_T(0),CLK,CD,'0','1'); Chip2/QC_T(0) <= ((LDW AND Chip2/QC(0) AND NOT Chip2/QB(0) AND NOT Chip2/QA(0)) OR (LDW AND NOT Chip2/QC(0) AND Chip2/QB(0) AND Chip2/QA(0))); FDCPE_Chip2/QW0: FDCPE port map (Chip2/QW(0),Chip2/QW_D(0),CLK,CD,'0','1'); Chip2/QW_D(0) <= NOT (((LDW AND NOT Chip2/QW(1)) OR (NOT LDW AND NOT Chip2/QW(0)))); FDCPE_Chip2/QW1: FDCPE port map (Chip2/QW(1),Chip2/QW_D(1),CLK,CD,'0','1'); Chip2/QW_D(1) <= NOT (((LDW AND NOT Chip2/QW(2)) OR (NOT LDW AND NOT Chip2/QW(1)))); FDCPE_Chip2/QW2: FDCPE port map (Chip2/QW(2),Chip2/QW_D(2),CLK,CD,'0','1'); Chip2/QW_D(2) <= NOT (((LDW AND NOT Chip2/QW(3)) OR (NOT LDW AND NOT Chip2/QW(2)))); FDCPE_Chip2/QW3: FDCPE port map (Chip2/QW(3),Chip2/QW_D(3),CLK,CD,'0','1'); Chip2/QW_D(3) <= NOT ((LDW AND Chip2/QB(0)) XOR ((NOT LDW AND NOT Chip2/QW(3)) OR (LDW AND Chip2/QC(0) AND Chip2/QA(0)) OR (LDW AND NOT Chip2/QC(0) AND NOT Chip2/QA(0)))); FDCPE_Cout: FDCPE port map (Cout,Cout_D,CLK,CD,'0','1'); Cout_D <= NOT (((NOT Cout AND NOT LDS) OR (LDS AND NOT Chip2/QC(0)))); FDCPE_EOP: FDCPE port map (EOP,EOP_D,CLK,CD,'0','1'); EOP_D <= NOT (((NOT LDS AND NOT ST) OR (NOT LDS AND NOT EOP))); FDCPE_LDA1: FDCPE port map (LDA(1),LDA_D(1),CLK,CD,'0','1'); LDA_D(1) <= (ST AND Chip1/present_state_FSM_FFd6); FDCPE_LDS: FDCPE port map (LDS,LDS_D,CLK,CD,'0','1'); LDS_D <= (Chip2/Chip9/present_state(0) AND NOT Chip2/Chip9/present_state(2) AND CE AND Chip2/Chip9/present_state(1)); FDCPE_LDW: FDCPE port map (LDW,LDW_D,CLK,CD,'0','1'); LDW_D <= NOT (((NOT CE AND NOT LDA(1)) OR (Chip2/Chip9/present_state(0) AND NOT Chip2/Chip9/present_state(2) AND CE AND Chip2/Chip9/present_state(1) AND NOT LDA(1)))); FDCPE_S0: FDCPE port map (S(0),S_D(0),CLK,CD,'0','1'); S_D(0) <= NOT (((LDS AND NOT Chip2/QW(0)) OR (NOT LDS AND NOT S(0)))); FDCPE_S1: FDCPE port map (S(1),S_D(1),CLK,CD,'0','1'); S_D(1) <= NOT (((LDS AND NOT Chip2/QW(1)) OR (NOT LDS AND NOT S(1)))); FDCPE_S2: FDCPE port map (S(2),S_D(2),CLK,CD,'0','1'); S_D(2) <= NOT (((LDS AND NOT Chip2/QW(2)) OR (NOT LDS AND NOT S(2)))); FDCPE_S3: FDCPE port map (S(3),S_D(3),CLK,CD,'0','1'); S_D(3) <= NOT (((LDS AND NOT Chip2/QW(3)) OR (NOT LDS AND NOT S(3)))); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC2C256-7-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCCIO-1.8 2 EOP 74 KPR 3 B<1> 75 KPR 4 B<2> 76 KPR 5 B<3> 77 KPR 6 ST 78 KPR 7 A<0> 79 KPR 8 VCCAUX 80 KPR 9 A<1> 81 KPR 10 A<2> 82 KPR 11 KPR 83 KPR 12 KPR 84 VCC 13 KPR 85 KPR 14 KPR 86 KPR 15 KPR 87 KPR 16 KPR 88 KPR 17 KPR 89 GND 18 KPR 90 GND 19 KPR 91 KPR 20 KPR 92 KPR 21 KPR 93 VCCIO-1.8 22 KPR 94 KPR 23 KPR 95 KPR 24 KPR 96 KPR 25 KPR 97 KPR 26 KPR 98 KPR 27 VCCIO-1.8 99 GND 28 KPR 100 KPR 29 GND 101 KPR 30 KPR 102 KPR 31 KPR 103 KPR 32 CLK 104 KPR 33 KPR 105 KPR 34 KPR 106 KPR 35 KPR 107 KPR 36 GND 108 GND 37 VCC 109 VCCIO-1.8 38 KPR 110 KPR 39 KPR 111 KPR 40 KPR 112 KPR 41 KPR 113 KPR 42 KPR 114 KPR 43 KPR 115 KPR 44 KPR 116 KPR 45 KPR 117 KPR 46 KPR 118 KPR 47 GND 119 KPR 48 KPR 120 KPR 49 KPR 121 KPR 50 KPR 122 TDO 51 KPR 123 GND 52 KPR 124 KPR 53 KPR 125 KPR 54 KPR 126 KPR 55 VCCIO-1.8 127 VCCIO-1.8 56 KPR 128 KPR 57 KPR 129 KPR 58 KPR 130 KPR 59 KPR 131 KPR 60 KPR 132 KPR 61 KPR 133 KPR 62 GND 134 KPR 63 TDI 135 B<0> 64 KPR 136 A<3> 65 TMS 137 S<3> 66 KPR 138 S<2> 67 TCK 139 S<1> 68 KPR 140 S<0> 69 KPR 141 VCCIO-1.8 70 KPR 142 Cout 71 KPR 143 CD 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin KPR = Unused I/O with weak keeper (leave unconnected) WPU = Unused I/O with weak pull up (leave unconnected) TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin VCCAUX = Power supply for JTAG pins VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I VCCIO-1.8 = I/O supply voltage for LVCMOS18 VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I VREF = Reference voltage for indicated input standard *VREF = Reference voltage pin selected by software GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc2c256-7-TQ144 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Set Unused I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Enable Input Registers : ON Function Block Fan-in Limit : 38 Use DATA_GATE Attribute : ON Set Tristate Outputs to Termination Mode : KEEPER Default Voltage Standard for All Outputs : LVCMOS18 Input Limit : 32 Pterm Limit : 28