PLA#1.1 on the design of standard logic circuits
Individual for the next Lab #4 (due date 07/10):
Specify, plan, develop and test the Problem 2.6, a wind direction compass based on a combinational circuit.
This is a sample template to organise your report.
- Section 1 (4p): Specifications and questions from 1 to 11. This is Proteus circuit for experimenting. This is an example truth table deduced playing with the circuit and studying the Fig. 17.
- Section 2 (1p): Choose a plan for the wind_meter chip (each cooperative group member will be given a plan):
- Plan A (12). Project location L:\CSD\P2\wind_compassA\wind_compass.vhd
- Plan B (13). Project location L:\CSD\P2\wind_compassB\wind_compass.vhd
- Sections 3 (2.5p): Develop (14). Xilinx ISE, target chip: Spartan-3E XC3S500E-FG320
- Section 4 (2.5p): Test and verify (15). wind_compass_tb.vhd. ISim Xilinx ISim. You can capture the screen of the timing diagram using the "Snipping Tool" or similar.
PLA#1.2 on the design of arithmetic circuits and propagation time measurement
Teamwork in cooperative groups for the next Lab #6 (due date 21/10):
complete the circuit named Selectable _add_subt_comp_10bit represented in Fig. 1. Remember that the Comp_1bit is completely developed in its tutorial using the plan A and SoP. Many other files for adding and subtracting are available in P4 and P3.
Even cooperative groups: solve the component Comp_1bit using plan A and only_NOR equations.
Odd cooperative groups: solve the component Comp_1bit using plan B. Be aware that because this is a combinational circuit, whatever to be translated to VHDL to synthesise has to generate an RTL schematic with no inferred latches or memory devices (examine the synthesis report).
Fig. 1. The entity for the PLA#1.2. |
This is a sample template to organise your report.
The main idea behind this hierarchical design is, once the project has been understood top --> botom, to proceed bottom --> top solving several subprojects to design the required components in each architectural layer.
For example, the comparator subsection of the project can be subdivided in:
Project 1) Solve as usual (S, P, D, T) the component Comp_1bit as stated above for even and odd groups. I you don't find the solution, copy the SoP files from the Comp_1bit tutorial to go ahead with the next project.
Project 2) Solve the Comp_10bit. Natural (whole) numbers in radix-2. This is an idea of a plan.
Project 3) Solve the Int_comp_10bit for integers in 2C. This is an idea on how to deduce an algorithm and therefore the final plan.
Project 4) Solve the Selectable_comp_10bit in problem 4.4. The input N decides which data type to compare: natural or integer numbers. This is the conceptual idea of a circuit for two data types. How the final plan may look like if only one Comp_10bit is desired?
For example, the adder and subtractor can be subdivided in:
Project 5) Using the Adder_10bit developed in Lab#5 session and the Int_add_subt_8bit from P4, solve the project Int_add_subt_10bit. Integers in 2C.
Project 6) Solve the project Selectable_add_subt_10bit. The input N decides which data type to add or subtract: natural or integer numbers. This is the conceptual idea and a possible plan.
And, finally, combine the selectable comparator and adder-subtractor in the entity represented in Fig.1:
Project 7) Solve the project Selectable_add_subt_comp_10bit.
Solving projects in cooperative groups is not easy, on the contrary. Thus, clarify which task each team mate has to do and is responsible for, in which time the task has to be done, and how are you assuring that everybody learns all the project sections. Discuss extensively the problem (specifications and plan) with your team mates and instructors using pen & paper and some numbers to test before starting the developing and verification using the EDA tools. Remember that the VHDL has no value unless there is a detailed original plan. |
Note: The measurement of the operational speed of the synthesised circuit can be performed in any of previous projects using the gate-level simulator.
PLA#2.1 on 1-bit memory cells and FSM
Individual for the next Lab #7 (due date 11/11):
(review) Problem 5.4: Specifications and theory on the JK_FF. Planning and designing the JK_FF as a FSM (P5 project). And also learning how the 1-bit memory cells work when used in a circuit, for instance an asynchronous one. Design and test in VHDL the circuit below.
Fig 2. An asynchronous circuit based on JK_FF. |
Organise the solution as follows:
Sections a, b, e --> 6p. Solve the problem theoretically in paper. Sections c and d were already solved and studied in previous preliminary exercises on P5, so you've already got the JK_FF.vhd file now). If you have problems deducing the timing diagram of the circuit in Fig. 33, you can try first the problem 5.7 or another similar asynchronous circuit. Here the aim is to learn how to deal with several clocks and the difficulties of asynchronous circuits. You can help yourself using Proteus because you have similar circuit that can be modified conveniently.
Section e --> 4p . Develop and test in VHDL the circuit in Fig. 33 to see if it works as expected or not.
This is a sample template to organise your report.
PLA#2.2 on counters and registers
Teamwork for the next Lab #9 (due date 25/11):
(review)
Odd coopertive groups --> Problem 7.8: Johnson counter using the plan Z. Marks: a, e, f --> 5p; g, h, i, j --> 5p.
Even cooperative groups --> Problem 6.7: Digit sequencer based on a FSM. Marks: 1 - 5 --> 5p; 6 -8 --> 5p.
This is a sample template to organise your report.
Please, maximase your chances for getting better grades, learn from your previous experience solving projects in cooperative groups: which you know that it is not an easy task: discuss extensively the problem (specifications and plan) with your team mates and instructors using pen & paper before starting the developing and test. And clarify which job does each team mate and how are you assuring that everybody learns all the project sections.
PLA#3.1 on microcontroller circuits
Individual for the next Lab #11 (due date 9/12)
(review) Problem 9.3: Solve a 1-digit BCD adder that includes 7-segment displays and LED to represent results.
The problem is reviewed and assessed in this way: half of the project, sections 1 and 2, is prepared in classrooms using paper and group discussions. The last sections 3 and 4 are solved by means of the virtual laboratory (IDE �€“ Simulator) available from our virtual desktop computers.
Remember that each of you have access to your personal network disk (L:) in the virtual desktop to properly develop and test your own project.
- Specifications and planning 5p.
- Interactive development and test 5p.
This is a sample template to organise your report.