PLA#1.1 on the design of standard logic circuits
Individual for the next Lab #4: (Due date 08/03)
Specify, plan, develop and test the Problem 2.4, a keypad encoder based on a combinational circuit. Thus, we'll be able to compare it with the matrix keypad encoder project proposed by W7 as the P6.
This is a sample template to organise your report.
- Section 1 (4p): Specifications and questions from 1 to 8.
- Section 2 (1p): Choose a plan for the Enc_10_4 chip:
- Odd cooperative groups --Plan A (11). Project location L:\CSD\P2\Enc_10_4A\Enc_10_4.vhd
- Even cooperative groups --Plan B (12). Project location L:\CSD\P2\Enc_10_4B\Enc_10_4.vhd
- Sections 3 (2.5p): Develop (14). Quartus II, target chip: Cyclone III 3C16F484C6N
- Section 4 (2.5p): Test and verify (15). Enc_10_4_tb.vhd. ModelSim Altera. You can capture the screen of the timing diagram using the "Snipping Tool"
HINT: In this Q#1.1 questionnaire sample there is a question on an encoder which has a similar truth table, and for instance, perhaps the MUX_8 plan B schematic (2) and its VHDL translation (2) using the "std_match" statement for the dont' care "-" terms is a good idea to copy & adapt in order to get your Enc_10_4.vhd source file.
PLA#1.2 on the design of arithmetic circuits
Teamwork in cooperative groups for the next Lab #6: (Due date 22/03)
Solve the design proposed in Problem 4.4
Even groups: solve the component Comp_1bit using plan A and only_NOR equations (let's try again because many of you have failed the question 8 in PLA#1.1 on circuits based on only_NAND or only_NOR). So, keep an eye on it.)
Odd groups: solve the component Comp_1bit using plan B. Be aware that, because this is a combinational circuit, whatever to translate to VHDL to develop has to generate an RTL schematic with no inferred latches or memory devices (examine the synthesis report).
Fig 1. Project symbol. |
This is a sample template to organise your report.
The main idea behind this hierarchical design is, once the project has been undertood, to go from bottom to top: 1) Solve and test completely the component Comp_1bit. 2) Solve completelly and test the Comp_8bit based on Comp_1bit. 3) Solve completelly the Comp_2C_8bit based on Comp_8bit and other circuits, and use it to deduce how to implement and test the Integer_comp_8bit.
PLA#2.1 on 1-bit memory cells and FSM
Individual for the next Lab #7: (Due date 12/04)
Problem 5.4: Specifications and theory on the JK_FF. Planning and designing the JK_FF as a FSM (P5 project). And also learning how the 1-bit memory cells work when used in a circuit, for instance an asynchronous one. Design and test in VHDL the circuit below.
Fig 2. An asynchronous circuit based on JK_FF. |
Organise the solution as follows:
Sections a, b, e --> 6p. Solve the problem theoretically in paper. Sections c and d were already solved and studied in previous preliminary exercises on P5, so you've already got the JK_FF.vhd file now). If you have problems deducing the timing diagram of the circuit in Fig. 33, you can try first the problem 5.7 or another similar asynchronous circuit. Here the aim is to learn how to deal with several clocks and the difficulties of asynchronous circuits. You can help yourself using Proteus because you have similar circuit that can be modified conveniently.
Section e --> 4p . Develop and test in VHDL the circuit in Fig. 33 to see if it works as expected or not.
This is a sample template to organise your report.
PLA#2.2 on counters and registers
Teamwork for the next Lab #9: (Due date 03/05).
Odd coopertive groups --> Problem 7.8: Johnson counter using the plan Z. Marks: a, e, f --> 5p; g, h, i, j --> 5p.
Even cooperative groups --> Problem 6.7: Digit sequencer based on a FSM. Marks: 1 - 5 --> 5p; 6 -8 --> 5p.
PLA#3.1 on microcontroller circuits