Archive of CSD exams, questions, problems and assessment mechanism |
In this course practically all lecturing, laboratory, guided activities and study time is for solving projects in this fashion:
1. Specifications, 2. Planning, 3. Development and 4. Test.
You are encouraged to write reports for the designed circuits, finishing as much exercises as you can and show them to us for correction and discussion. Because writing original reports is the best way to learn deeply the course content and put into practice cross-curricular skills.
- This is a sample set of questions for questionnaire Q#1.1 on P1 and P2 projects.
- This is a sample set of questions for questionnaire Q#1.2 on P3 and P4 projects (remember that P1 and P2 are also included).
- This is a sample set of questions for questionnaire Q#2.1 on P5 and P6 projects (remember that P1, P2, P3 and P4 are also included).
Some selected exam assignments, tutorial projects and questions are conveniently rewritten as projects in our collection:
- Docx
Examples of mid-term exams (Exa_1)
- 1819Q2. This is the exam EX1 (pdf) and sample solutions (Prob. 1 option B is here as the Circuit_B).
- 1819Q1. This is the exam EX1 (pdf) and commented solutions (P1) (P2).
- 1718Q2. This is the exam EX1 (pdf) and a discussed solution. This is the Problem 1 truth table in Minilog format.
- 1718Q1. This is the exam EX1 (pdf) and a Proteus simulation to experiment the way it works, and a possible solution. The Gray_Bin_Converter (Chip1) in Minilog format.
- 1617Q2. This is an example exercise IT1 (pdf) that contains many concepts develop since now through P1 .. P4. This is the Proteus file, the truth table in Minilog and the results when simplifying by PoS. This is the discussion on the problem solved some years ago.
- 1617Q2. This is another similar exercise IT1r (pdf). The truth table, the Minilog result, and the symbol in Proteus that can be simulated attaching this "jed" to the AM22V10 sPLD. This is a possible VHDL file (question 5), and this is the ispLEVER Classic report where you see the pin connections after synthesising the circuit.
- 1617Q1.
Examples of final-term exams (Exa_2)
- 1819Q1. This is the exam EX2 (pdf) and example solutions (P1) (P2).
- 1718Q2. This is the exam EX2 (pdf) and a draft solution example (P1, P2, P3).
- 1718Q1. This is the exam EX2 (pdf) and a draft solution example.
- 1617Q2.
- 1617Q1.
Assessment of student achievement
This is the CSD spreadsheet to calculate student partial and final grades. You can use it to follow your own performance. For instance:
D_Ch1 => 15 % => 5%·Q#1.1 + 5%·Q#1.2 + 2.5%·PLA#1.1 + 2.5%·PLA#1.2
D_Ch2=> 15 % => 5%·Q#2.1 + 5%·Q#2.2 + 2.5%·PLA#2.1 + 2.5%·PLA#2.2
D_Ch3 => 20 % = 2.5%·PLA#3.1 + 5%·Q#3.1 + 12.5%·P_Ch3 [Group project: 10% Oral presentation + 2.5%· Written Report]
EXA1 = 20%, EXA2 = 20%
ActP = 10% in function of the number of D_Ch (25%) and exams (25%) passed and laboratory class attendance (50%).