Entering state transition tables
================================
The input for the minimizer is a textfile,
composed with any ASCII editor like Notepad.
Allowed separators are any combinations of
white spaces, comma's, semicolons (;) or vertical
bars (|). No distinction is made between
uppercase and lowercase characters.
The first line should contain the reserved
word 'TABLE' followed by the name of the function
table to be minimized.
The next lines contain the names of the
primary inputs and outputs of the network, starting
with the reserved words 'INPUT' or
'OUTPUT'. Both input and output variables are limited to a
number of 40, more than one INPUT or
OUTPUT line is allowed.
The length of the input and output names
is limited to 8 characters, for the generation of
Faultsim netlists or schematic diagrams it
is strongly recommended to limit those identifiers
to no more than 6 characters.
If the function must be implementated in a
PLD some directives concerning the device type and
the pin assignment to ABEL can be placed
immediately after the INPUT and OUTPUT lines, all
starting with #. These ABEL directives,
that are ignored for all other output formats, must
include the flipflop output names
"Qi" with i ranging from 0 to the state vector length minus
1, the clock pin "FF.CLK" and if
applicable the asynchronous reset pin "FF.AR". If the device,
that is being used, contains other
flipflop control signals, the generated ABEL input file has
to be completed afterwards by editing it.
The following line should contain the word
'STATES', after which the state table follows.
This table records the state symbols and
the belonging binary state code.
The state symbol is an identifier with a
maximal length of 4 characters. As always, no
distinction is made between uppercase and
lowercase characters. The code is entered with
the most significant bit first.
Specification of don't care states may be necessary for an
optimal result. From Minilog version 4.61
on using periods '.' in the state code is possible,
idicating non-specified values.
Empty lines are ignored, while lines
starting with double quotes (") are treated as comment.
The states table is completed with an
'END' line, after which the state transition table
follows, completed with 'END' as well. A
line consists of the prior state symbol followed
by an optional input vector and the next
state symbol with an optional output vector.
The state-register element names QN...Q0
cannot be used as output signal name. If the state
register output is required as primary
circuit output, as is usually the case for counters,
the State Register Output option must be
selected in combination with the Faultsim Netlist
or Schematic Drawing output format.
In the case of the default multiple-output
minimization a MOORE-type state machine might be
turned into a MEALY-type. The primairy
output function remains, however, independent of the
primary inputs, but the multiple-output
minimization may introduce some dynamic dependence.
Use the Moore Enforcement whenever a
MOORE-type result must be guaranteed.
All options, documented for the
combinational functions in the Boolean Function Tables
section, can be used for state machines as
well.
Having recognized the STATES line, the
program will utilise the selected flip-flop type to
generate the excitation vectors belonging
to the desired state transitions automatically.
The flipflop outputs are indicated with
'Q', the inputs with '_D', '_T', '_J', '_K', '_S'
or '_R', followed by the order number.
Don't use these identifiers in the list of primary
inputs or outputs.
The state expansion must not lead to more
than 40 input or 40 output variables in the
excitation table.
An example is found in the file
"counter.tbl". Try a minimalisation with several types of
flip-flops and notice the difference in
the complexity of the logic circuits needed to
realise the counter.
table counter
input enab up
output co
" ABEL device and pin assignment lines starting
with #
# device p22v10 " for ABEL output format only
# pins 3=enab 4=up 17=co " for ABEL output format only
# pins 14=Q2 15=Q1 16=Q0 " flipflop outputs Qn-1 ... Q0
# pins 1=FF.clk 2=FF.ar " clock and asynchronous reset
states
" state vector encoding
qa 000
qb 001
qc 010
qd 011
qe 100
qx 101 " unused state code
qy 11- " unused state codes (both 110 and
111)
qz --- " don't care (next) state code
end
" PS Inputs NS
Outputs
qa 0- | qa
0
qa 11 | qb 0
qa 10 | qe 1
qb 0- | qb 0
qb 11 | qc 0
qb 10 | qa 0
qc 0- | qc 0
qc 11 | qd 0
qc 10 | qb 0
qd 0- | qd 0
qd 11 | qe 0
qd 10 | qc 0
qe 0- | qe 0
qe 11 | qa 1
qe 10 | qd 0
qx -- | qz -
" assign all unused state codes
qy -- | qz -
" to the don't care cover
end
A second example in the file "register.tbl"
shows the use of periods in the state code and
the output vector for describing a 2-bit
register consisting of two completely independent
cells. Notice the way each of the register
cells is considered as a one-bit/two-states
state machine. The outputs may be omitted
as well as both output columns if the Minilog
State Register Output option is to be used
alternatively.
table Register
input Load Din[1] Din[0]
output Dout[1] Dout[0]
states
" Register cell 1
S10 0.
S11 1.
" Register cell 0
S00 .0
S01 .1
End
" PS Inputs
NS Outputs
" Storing cell 1
S10 0 -- S10 0.
S11 0 -- S11 1.
" Loading cell 1
S10 1 0- S10
0.
S10 1 1- S11
0.
S11 1 0- S10
1.
S11 1 1- S11
1.
" Storing cell 0
S00 0 -- S00
.0
S01 0 -- S01
.1
" Loading cell 0
S00 1 -0 S00
.0
S00 1 -1 S01
.0
S01 1 -0 S00
.1
S01 1 -1 S01
.1
end