Minimizing combinational function tables

========================================

 

The table file "Bcd_7seg.tbl", as described in the section "Boolean Function Tables", will be

used as an example to describe the minimization process.

 

                   table bcd-7segment_decoder

                     input qd qc qb qa

                     output a b c d

                     output e f g

                   " ABEL device and pin assignment lines starting with #

                   # device p16L8             " for ABEL output format only

                   # pins 1=qd 2=qc 3=qb 4=qa " for ABEL output format only

                   # pins 12=a 13=b 14=c 15=d " for ABEL output format only

                   # pins 16=e 17=f 18=g      " for ABEL output format only

                     0000 , 1 1 1 1 1 1 0

                     0001 , 0 1 1 0 0 0 0

                     0010 , 1 1 0 1 1 0 1   "       -- a --

                     0011   1 1 1 1 0 0 1   "      |       |

                     0100 ; 0 1 1 0 0 1 1   "      f       b

                     0101 ; 1 0 1 1 0 1 1   "      |       |

                     0110 ; 0 0 1 1 1 1 1   "       -- g --

                     0111   1 1 1 0 0 0 0   "      |       |

                     1000   1 1 1 1 1 1 1   "      e       c

                     1001 | 1 1 1 0 0 1 1   "      |       |

                     101- | - - - - - - -   "       -- d --

                     11-- | - - - - - - -

                   end

 

Select the table file using the Open option in the Files menu and Run the Minimizer. The table

is read and checked for completeness and errors and is minimized. The minimized result, using

the default program options, is presented onto the screen as well as in the file "bcd_7seg.min"

and will look like:

 

             MINIMIZATION RESULT STATISTICS

             ==============================

             FOUND 9 ESSENTIAL PRODUCT TERMS

             MAXIMUM FANIN:                7

             TOTAL LITERAL COUNT:          50

             MAXIMUM PRODUCT TERM SIZE:    3

             MAXIMUM OUTPUT FUNCTION SIZE: 5

 

                   ==============

                   QQQQ

                   DCBA   ABCDEFG

                   ==============

                   --10 | ...11..

                   -1-0 | ..1..11

                   -0-0 | 1..11..

                   --00 | .1...1.

                   -00- | .11....

                   -101 | 1.11.11

                   -01- | .1.1..1

                   --11 | 111....

                   1--- | 1....11

 

The minimized table specifies all essential product terms (factors in case of product of sums

minimization) and the output functions in which these are active.

 

The above table translated into logic equations:

 

      A = QC'.QA' + QC.QB'.QA + QB.QA + QD

      B = QB'.QA' + QC'.QB' + QC'.QB + QB.QA

      C = QC.QA' + QC'.QB' + QC.QB'.QA + QB.QA

      D = QB.QA' + QC'.QA' + QC.QB'.QA + QC'.QA

      E = QB.QA' + QC'.QA'

      F = QC.QA' + QB'.QA' + QC.QB'.QA + QD

      G = QC.QA' + QC.QB'.QA + QC'.QB + QD

 

 

Faultsim Netlist output format

==============================

 

The Faultsim Netlist option can be used to obtain a FAULTSIM netlist, a convenient way to

verify the design correctness or to generate a set of test vectors. Be sure that the first 6

characters of the identifiers designate the input and output variables uniquely, to avoid

problems during the FAULTSIM execution. Using identifiers containing more than 6 characters

will give rise to a warning. Optionally a library can be specified, in order to restrict the

maximum number of gate inputs. Use the same library as with the Schematic Drawing output format

for the netlist to be identical to the schematic.

 

An optional Netlist Node Extension of maximally 2 characters may be specified, that will be

concatinated to all internal nodes within the netlist. This will uniquely identify the internal

nodes of any logic network.

 

In addition to either the Faultsim Netlist or the Schematic Drawing output format, by the

Inverted Gate Polarity option the generated netlist or schematic can be optimized in terms of

speed and space by using as many inverting gates as possible. The result remains, however, a

two layer implementation of the logic circuit.

 

Example of such a produced netlist in the file "Bcd_7seg.net":

 

             NETLIST BCD-7SEGMENT_DECODER

             " Generated by Minilog on Monday, May 15, 1989; 15:31

             INPUT QD QC QB QA

             OUTPUT A B C D E F G

             N_QD INV QD

             N_QC INV QC

             N_QB INV QB

             N_QA INV QA

             NET1 AND QB N_QA

             NET2 AND QC N_QA

             NET3 AND N_QC N_QA

             NET4 AND N_QB N_QA

             NET5 AND N_QC N_QB

             NET6 AND QC N_QB QA

             NET7 AND N_QC QB

             NET8 AND QB QA

             NET9 BUF QD

             A OR NET3 NET6 NET8 NET9

             B OR NET4 NET5 NET7 NET8

             C OR NET2 NET5 NET6 NET8

             D OR NET1 NET3 NET6 NET7

             E OR NET1 NET3

             F OR NET2 NET4 NET6 NET9

             G OR NET2 NET6 NET7 NET9

             END

 

 

Schematic Drawing output format

===============================

 

If the program has been correctly installed to cooperate with the ispTOOLS design package from

Lattice Semiconductor, by means of the Schematic Drawing output format a schematic diagram can

be obtained.  The specification of a library is required. This library file contains

information regarding the gates, like e.g. the number of inputs, the topological symbol data

and the names, must have an extension ".lib" and should either reside in the MINILOG

executable directory or in the library directory specified by the MINILOG_PATH option in the

config file "Minilog.cfg".

 

The below schematic diagram can now be found in the file "Bcd_7seg.sch" with its belonging

symbol in "Bcd_7seg.sym".

 

   

 

In addition to either the Faultsim Netlist or the Schematic Drawing output format, by the

Inverted Gate Polarity option the generated netlist or schematic can be optimized in terms of

speed and space by using as many inverting gates as possible. The result remains, however, a

two layer implementation of the logic circuit.

 

 

Logic Equations output format

=============================

 

The output can be presented in the form of such logic equations by the Logic Equations output

format in the file "Bcd_7seg.equ". Writing all signal names in full, however, would lead to

very long, badly arranged expressions. Therefore the variables are designated by single

characters, the inputs from 'A' and the outputs up to 'Z', limiting the total number of

input plus output variables to 26.

 

The minimized equations are preceded bij a variable translation table.

 

Example using the Logic Equations output format:

 

             MINIMIZATION RESULT STATISTICS

             ==============================

             FOUND 9 ESSENTIAL PRODUCT TERMS

             MAXIMUM FANIN:                7

             TOTAL LITERAL COUNT:          50

             MAXIMUM PRODUCT TERM SIZE:    3

             MAXIMUM OUTPUT FUNCTION SIZE: 5

 

             INPUT SIGNAL  |  OUTPUT SIGNAL  REPRESENTATION

 

             A : QD             |       T : A         X : E

             B : QC             |       U : B         Y : F

             C : QB             |       V : C         Z : G

             D : QA             |       W : D

 

             MINIMIZED EQUATIONS

 

             T = B'D' + BC'D + CD + A

             U = C'D' + B'C' + B'C + CD

             V = BD' + B'C' + BC'D + CD

             W = CD' + B'D' + BC'D + B'C

             X = CD' + B'D'

             Y = BD' + C'D' + BC'D + A

             Z = BD' + BC'D + B'C + A

 

 

ABEL output format

==================

 

Selecting the ABEL output format will cause an ABEL input file to be generated having the

file name extension ".abl", containing all supplied information for the PLD-implementation of

the design if immediately after the INPUT and OUTPUT lines the device-type is specified and

all pins assigned. Of course the ABEL file can be edited afterwards, e.g. to enter the test

vectors. By the ABEL_DEVICE_DATA option in the configuration file MINILOG.CFG the way this

device data is dealt with can be customized.

 

             Module BCD-7SEGMENT_DECODER

             Title        'Minilog table: bcd_7seg.tbl'

             PAL device   'P16L8';

             " Generated by Minilog 4.5 on Wednesday, October 6, 2004; 02:24

 

             QD             pin 1 ;

             QC             pin 2 ;

             QB             pin 3 ;

             QA             pin 4 ;

             A              pin 12 ;

             B              pin 13 ;

             C              pin 14 ;

             D              pin 15 ;

             E              pin 16 ;

             F              pin 17 ;

             G              pin 18 ;

 

             h,l,z,c,x = 1,0,.z.,.c.,.x.;

 

 

             " MINIMIZATION RESULT STATISTICS

             " ==============================

             " FOUND 9 ESSENTIAL PRODUCT TERMS

             " MAXIMUM FANIN:                7

             " TOTAL LITERAL COUNT:          50

             " MAXIMUM PRODUCT TERM SIZE:    3

             " MAXIMUM OUTPUT FUNCTION SIZE: 5

             " INDIVIDUAL OUTPUT FUNCTION SIZE:

             "     1:         A              4

             "     2:         B              4

             "     3:         C              5

             "     4:         D              4

             "     5:         E              2

             "     6:         F              5

             "     7:         G              5

 

             Equations

 

             A = QB&QA # !QC&!QA # QC&!QB&QA # QD;

             B = !QC&!QB # QB&QA # !QC&!QA # QC&!QB&!QA;

             C = !QC&!QB # QB&QA # QC&!QB&!QA # QC&QB&!QA # QC&!QB&QA;

             D = !QC&!QB&!QA # !QC&QB # QC&QB&!QA # QC&!QB&QA;

             E = !QC&!QA # QC&QB&!QA;

             F = !QC&!QB&!QA # QC&!QB&!QA # QC&QB&!QA # QC&!QB&QA # QD;

             G = !QC&QB # QC&!QB&!QA # QC&QB&!QA # QC&!QB&QA # QD;

 

             Test_vectors ([QD,QC,QB,QA]

                        -> [A,B,C,D,E,F,G])

 

             End BCD-7SEGMENT_DECODER