Minimizing state
machine tables
===============================
The table file
"Counter.tbl", as described in the section "State Transition
Tables", will be
used as an
example to describe the minimization process.
table counter
input enab up
output co
" ABEL device and pin
assignment lines starting with #
# device p22v10 " for ABEL output format only
# pins 3=enab 4=up 17=co " for ABEL output format only
# pins 14=Q2 15=Q1 16=Q0 " flipflop outputs Qn-1 ... Q0
# pins 1=FF.clk 2=FF.ar " clock and asynchronous reset
states " state vector encoding
qa 000
qb 001
qc 010
qd 011
qe 100
qx 101 " unused
state code
qy 11- " unused state codes (both 110 and
111)
qz --- " don't care
(next) state code
end
" PS Inp NS Outp
qa 0- qa 0
qa 11 qb 0
qa 10 qe 1
qb 0- qb
0
qb 11 qc 0
qb 10 qa 0
qc 0- qc 0
qc 11 qd 0
qc 10 qb 0
qd 0- qd 0
qd 11 qe 0
qd 10 qc 0
qe 0- qe 0
qe 11 qa 1
qe 10 qd 0
qx -- qz -
" assign all unused state
qy -- qz -
" codes to don't care cover
end
Select the table
file using the Open option in the Files menu and Run the Minimizer using the
default
settings. The table is read and checked for completeness and errors and is
minimized.
The minimized
result is presented onto the screen as well as in the file
"counter.min" and
will look like:
MINIMIZATION RESULT STATISTICS
==============================
FOUND 12 ESSENTIAL PRODUCT TERMS
MAXIMUM FANIN: 10
TOTAL LITERAL COUNT: 52
MAXIMUM PRODUCT TERM SIZE: 5
MAXIMUM OUTPUT FUNCTION SIZE: 5
============
E
N ___
QQQAU DDDC
210BP 210O
============
00010 | 1..1
0-011 | ..1.
-0111 | .1..
-1111 | 1...
-10-1 | .1..
-11-0 | .1..
1--11 | ...1
1--0- | 1...
-101- | ..1.
--10- | ..1.
1--10 | .11.
-1-0- | .1..
The minimized
table specifies all essential product terms (factors in case of product of sums
minimization)
and the output functions in which these are active. The three leftmost columns
contain the
flipflop outputs, designated by the reserved names Q2, Q1 and Q0. Next come the
two primary
inputs ENAB and UP. The output part of the table contains the flipflop input
signals _D2, _D1
and _D0 as well as the primary output signal CO.
The above table
translated into logic equations:
_D2 = Q2'.Q1'.Q0'.ENAB.UP' + Q2.ENAB.UP
_D1 = Q1'.Q0.ENAB.UP + Q1.Q0'.UP +
Q1.Q0.UP' + Q2.ENAB.UP' + Q1.ENAB'
_DO = Q2'.Q0'.ENAB.UP + Q1.Q0'.ENAB +
Q0.ENAB' + Q2.ENAB.UP'
C0 = Q2'.Q1'.Q0'.ENAB.UP' + Q2.ENAB.UP
Faultsim Netlist
output format
==============================
The Faultsim
Netlist option can be used to obtain a FAULTSIM netlist, a convenient way to
verify the
design correctness or to generate a set of test vectors. Be sure that the first
6
characters of
the identifiers designate the input and output variables uniquely, to avoid
problems during
the FAULTSIM execution. Using identifiers containing more than 6 characters
will give rise
to a warning. Optionally a library can be specified, in order to restrict the
maximum number
of gate inputs. Use the same library as with the Schematic Drawing output
format
for the netlist
to be identical to the schematic.
An optional
Netlist Node Extension of maximally 2 characters may be specified, that will be
concatinated to
all internal nodes within the netlist. This will uniquely identify the internal
nodes of any
logic network.
By selecting the
State Register Output option the flipflop outputs will be appended to the set
of primary
outputs. This may prevent errors due to using internal signal names for primary
inputs or
outputs.
In addition to
either the Faultsim Netlist or the Schematic Drawing output format, by the
Inverted Gate
Polarity option the generated netlist or schematic can be optimized in terms of
speed and space
by using as many inverting gates as possible. The result remains, however, a
two layer
implementation of the logic circuit.
Example of such
a produced netlist, using the Inverted Gate Polarity option, the State Register
Output option as
well as the Netlist Node Extension set to "xx" in the file
"Counter.net":
NETLIST COUNTER
" Generated by Minilog on
Monday, May 15, 1989; 15:40
INPUT ENAB UP
OUTPUT QXX2 QXX1 QXX0 "State Register Output
OUTPUT CO
N_ENAB INV ENAB
N_UP INV UP
QXX2 DFF _DXX2
N_QXX2 INV QXX2
QXX1 DFF _DXX1
N_QXX1 INV QXX1
QXX0 DFF _DXX0
N_QXX0 INV QXX0
NETXX1 NAND N_QXX2 N_QXX1 N_QXX0
ENAB N_UP
NETXX2 NAND N_QXX2 N_QXX0 ENAB
UP
NETXX3 NAND N_QXX1 QXX0 ENAB
UP
NETXX4 NAND QXX1 QXX0 ENAB
UP
NETXX5 NAND QXX1 N_QXX0 UP
NETXX6 NAND QXX1 QXX0 N_UP
NETXX7 NAND QXX2 ENAB UP
NETXX8 NAND QXX2 N_ENAB
NETXX9 NAND QXX1 N_QXX0 ENAB
NETXX10 NAND QXX0 N_ENAB
NETXX11 NAND QXX2 ENAB N_UP
NETXX12 NAND QXX1 N_ENAB
_DXX2 NAND NETXX1 NETXX4
NETXX8
_DXX1 NAND NETXX3 NETXX5 NETXX6
NETXX11 NETXX12
_DXX0 NAND NETXX2 NETXX9 NETXX10
NETXX11
CO NAND NETXX1 NETXX7
END
Schematic
Drawing output format
===============================
If the program
has been correctly installed to cooperate with the ispTOOLS design package from
Lattice
Semiconductor, by means of the Schematic Drawing output format a schematic
diagram can
be
obtained. The specification of a
library is required. This library file contains
information
regarding the gates, like e.g. the number of inputs, the topological symbol
data
and the names,
must have an extension ".lib" and should either reside in the MINILOG
executable
directory or in the library directory specified by the MINILOG_PATH option in
the
config file
"Minilog.cfg". In this example the library "Generic_noscan.lib"
has been selected.
The below
schematic diagram can now be found in the file "Counter.sch" with its
belonging
symbol in
"Counter.sym".
By selecting the
State Register Output option the flipflop outputs will be appended to the set
of primary
outputs. This may prevent errors due to using internal signal names for primary
inputs or
outputs.
In addition to
either the Faultsim Netlist or the Schematic Drawing output format, by the
Inverted Gate
Polarity option the generated netlist or schematic can be optimized in terms of
speed and space
by using as many inverting gates as possible. The result remains, however, a
two layer
implementation of the logic circuit.
Logic Equations
output format
=============================
The output can
be presented in the form of such logic equations by the Logic Equations output
format in the
file "Counter.equ". Writing all signal names in full, however, would
lead to
very long, badly
arranged expressions. Therefore the variables are designated by single
characters, the
inputs from 'A' and the outputs up to 'Z', limiting the total number of
input plus
output variables to 26.
Example using
the Logic Equations output format:
MINIMIZATION RESULT STATISTICS
==============================
FOUND 12 ESSENTIAL PRODUCT TERMS
MAXIMUM FANIN: 10
TOTAL LITERAL COUNT:
52
MAXIMUM PRODUCT TERM SIZE: 5
MAXIMUM OUTPUT FUNCTION SIZE: 5
INPUT SIGNAL |
OUTPUT SIGNAL REPRESENTATION
A : Q2 D : ENAB
| W : _D2 Z : CO
B : Q1 E : UP
| X : _D1
C : Q0 |
Y : _D0
MINIMIZED EQUATIONS
W = A'B'C'DE' + BCDE + AD'
X = B'CDE + BC'E + BCE' + ADE' +
BD'
Y = A'C'DE + BC'D + CD' + ADE'
Z = A'B'C'DE' + ADE
ABEL output
format
==================
Selecting the
ABEL output format will cause an ABEL input file to be generated having the
file name
extension ".abl", containing all required information for the
PLD-implementation of
the design if
immediately after the INPUT and OUTPUT lines the device-type is specified and
all pins
assigned. Of course the ABEL file can be edited afterwards, e.g. to enter the
test
vectors. By the
ABEL_DEVICE_DATA option in the configuration file MINILOG.CFG the way this
device data is
dealt with can be customized.
By selecting the
State Register Output option the flipflop outputs will be appended to the set
of primary
outputs. This may prevent errors due to using internal signal names for primary
inputs or
outputs. By default the flipflop outputs are treated as internal nodes.
Module COUNTER
Title 'Minilog table: Counter.tbl'
PAL device 'P22V10';
" Generated by Minilog 4.5
on Monday, October 25, 2004; 19:45
cp pin 1 ;
ar pin 2 ;
ENAB pin 3 ;
UP pin 4 ;
CO pin 17 ;
Q2 pin 14 IsType 'Reg' ;
Q1 pin 15 IsType 'Reg' ;
Q0 pin 16 IsType 'Reg' ;
h,l,z,c,x = 1,0,.z.,.c.,.x.;
flipflops = [ Q2, Q1, Q0 ];
" MINIMIZATION RESULT
STATISTICS
"
==============================
" FOUND 12 ESSENTIAL PRODUCT
TERMS
" MAXIMUM FANIN: 10
" TOTAL LITERAL COUNT:
52
" MAXIMUM PRODUCT TERM
SIZE: 5
" MAXIMUM OUTPUT FUNCTION
SIZE: 5
" INDIVIDUAL OUTPUT FUNCTION
SIZE:
" 1: Q2 3
" 2: Q1 5
" 3: Q0 4
" 4: CO 2
Equations
flipflops.clk = cp;
flipflops.ar = ar;
Q2 :=
!Q2&!Q1&!Q0&ENAB&!UP # Q1&Q0&ENAB&UP #
Q2&!ENAB;
Q1 := !Q1&Q0&ENAB&UP
# Q1&!Q0&UP # Q1&Q0&!UP # Q2&ENAB&!UP # Q1&!ENAB;
Q0 := !Q2&!Q0&ENAB&UP
# Q1&!Q0&ENAB # Q0&!ENAB # Q2&ENAB&!UP;
CO =
!Q2&!Q1&!Q0&ENAB&!UP # Q2&ENAB&UP;
Test_vectors ([ENAB,UP]
-> [Q2,Q1,Q0,CO])
End COUNTER