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10-11 Q2

Exercises and problems

vert Sessions calendar  and approximate due dates for the exercises. Every class group will set up a give agenda of due dates for the exercises. And every class group will have its own agenda, so, follow your agenda to look for the latest class developments and indications from your instructors.

vert You can also contact us through the course blog  and participate actively in class.

Chapter 1

Combinational circuits  
Chapter 2

Finite state machines (FSM)
Chapter 3

Dedicated processors
Chapter 4

Microcontrollers
 EX1A        EX1B       EX1C EX2 EX3 EX4A                EX4B                  Application Project


Chapters 1: Combinational Circuits

boleta EX1A (docx)  (Fig.1 Visio chart) Introduction to the subject: our content and learning methods.

Write your solution starting the 1.6 Section in the assignment file. Rename your file as, for example: "Gx_CSD_EX1A.docx", being the Gx your cooperative group number. Upload this file as an attachment at your ePortfolio EX1A before the due date page once you have finished it.

vert Here you have a forum for discussion

vert Here you have a flowchart to install software (Visio)

soft

Instructions for installing Proteus --> (UNIT1.2)

vert Analysis of simple digital circuits (UNIT 1.3)

  • Here you have the example circuit from Fig.2, so that you can check that the Proteus installation is all right. Be aware that your instructor may have changed this design by another similar, please check your particular class group agenda. Once you have deduced its logic equations (section e), you can design another version for the same circuit using a different type of logic gates (for example only-NOR, Section g). Later on, in EX1B, you can implement another version for the same the circuit using a single sPLD like the GAL22V10 represented below.

 

  • Here you have another simple circuit which is analysed and its equations deduced (in this case a  MUX4: a 4-bit multiplexer or also named data selector). Be aware that, in this case, the circuit is considered large, more than 5 inputs, so, it is structured in elemental blocks, the MUX2)


boleta EX1B (docx) Your first circuits into a sPLD

vert Part 1. Analysis of a simple digital circuit based on logic gates (As in EX1A). So, repeat the analysis of another simple circuit to clarify your understanding on minterms, maxterms, logic gates, sum of products, products of sums, etc.

  • Here you are "classic" implementation of a HEX-7SEG decoder using logic gates. Compare the design with this one in which a sPLD has replaced all the discrete gates HEX-7SEG decoder. Run the simulations so that you will see how both circuits are functionally equivalent.

  • Here you can try the different ways to input signals to a Proteus simulation. Examine this projects:

  • The Proteus Project. Using stimulus signals scripted in EasyHDL (version 1). This is a very simple language which is used to apply test vectors to the circuit/unit under test (UUT)
  • The Proteus Project using stimulus signals scripted in EasyHDL (version 2) and busses to compact the wiring
  • The Proteus Project using stimulus signals scripted in EasyHDL (version 3) in graphical mode
  • The Proteus Project using stimulus signals scripted in EasyHDL (version 4) in graphical mode and using loops to simplify the scripting of test signals

 

vert Part 2: Installing EDA tools for Lattice chips and your first designs

  • Here you have a flowchart (Visio) to install Lattice software  to produce your firsts "*.jed" configuration files for the sPLD GAL22V10, the chip which can be simulated using Proteus:(UNIT 1.5)

simulation

  • Take a look at the sPLD GAL22V10 architecture: designing logic functions by the BUFFER/NOT - AND - OR method  (UNIT 1.6) (Visio)

gal

  • Design a simple or small project in ispLEVER Classic consisting of a single VHDL file, and go through all the design flow for sPLD GAL22V10. In Fig.2 you have a detailed flow chart.  (Problem's Section 1.6, h, proposes you the example of a 2-bit adder (the Proteus schematic)

  • Observe that you can choose between two approaches: behavioural or different structures derived from  the various sets of logic equations. Precisely here, you can learn about the minimiser Minilog (UNIT 1.8). Thus, different group members can synthesise different circuits from the same initial specifications

  • In case of designing a large circuit with many inputs and outputs, it's always much better to organise it as a modular hierarchical design where components are interconnected together by means of signals. Please, read the 4-bit adder example in UNIT 1.7, because it explains the process of instantiating components in a top VHDL design. At this introductory level, a component may be a small circuit which is designed through the process explained above in the flowchart.

vert  Part 3: Install the ActiveHDL from Aldec (UNIT 1.13A) and run the sample project to check the software.

  • Here you have a flowchart (Visio) to include VHDL functional and gate-level simulations using Lattice software. This is the professional way, and a lot more efficient than the Proteus approach. It can be generalised to any digital circuit. Gate-level simulations will be studied later on in EX1C.

lattice

  • Perform a functional simulation (UNIT 1.14A) of a simple circuit, so that you will replace the sPLD simulations using Proteus by another procedure which is valid for any PLD/FPFA chip

vert Part 4: On building an standard component (to be added to a library of intellectual property (IP)

  • Here you are another flow diagram (Visio, page 2), to recall, repeat, discuss and consolidate the design flow, which, on the other hand, will be kept the same in the next chapter on sequential systems.

FlowChartB

  • Remember the idea of the large circuit with many inputs and outputs. Plan your design hierarchically with multiple VHDL files, if you see it necessary, or in case you see that it's going to be easier than using a single VHDL file.


boleta EX1C (docx) On the design of a complex combinational circuit + CPLD / FPGA chips + gate-level simulation in ActiveHDL

This is essentially, one hour for discussing and devising an ALU architecture, and another hour for learning about how to implement a gate-level simulation of any synthesised circuit. The other study time is for carrying on the ALU design.

vert Part 1: Planning the ALU (Visio for Fig.1 ) ((Visio for Fig.2 )

vert Part 2: The bottom -up design including gate-level simulations

  • Here you are the RTL schematic produced by the Synplify of a simple 4MUX4 block

  • And here you are its gate-level simulation (UNIT 1.15A)

 


Chapters 2: Finite State Machines

boleta EX2 (docx) Designing simple finite state machines (FSM) applications 

Part 1: The basics of finite state machines  (Copied to Unit 2.3). This semester we have to design a synchronous 4-bit up counter  using the FSM style.


Part 2: Designing a frequency divider for the HDW LC4128V board (schematic). Open it and see its internal architecture composed of 4 components ( FREQ_DIV_50, FREQ_DIV_100, FREQ_DIV_2, T_FLIP_FLOP) [Solution June 2011]

board

- Unit 2.4 for the T-FF and Unit 2.5 for the frequency dividers.  

- Here in Unit 2.5, you have previous version of a 1-digit BCD counter written using another description style based on the ARITHMETIC library. So, the CC1 may implement the next state like this:

future_state <= present_state + 1;

- In order to design properly, everyone of your sequential designs have to follow this  structure (Visio):

design_flow



In everyone of your projects use the Synplify or the ispLEVER tool (Fitter report) to check the number of registers (flip-flops) used. It have to agreed with your calculations. For example, a modulo-150 synchronous binary counter, designed following our architecture, have to have 8 flip-flops. If your design have more or less, it means that it is wrong, having inferred unwanted latches  or missed some states ....

registers

report

Here you are an example solution: These are waveforms showing the squared 1 Hz and the pulsed 4 Hz signals:

result

These are the higher frequency signals of the CLK and the 20 KHz:

20kHz

  • Some class recordings on the design of the frequency dividers at the Nadim El Taha ePortrfolio

  • Project files on May 20


Part 3: Designing standard sequential components

Each instructor will propose its own design for the part.

Part 4: Choose an application to develop:

Each instructor will propose its own design for the part.

 


Chapters 3: Dedicated processors

boleta EX3 (Docx for the Traffic Light Controller) (Docx for the Serial Multiplier)

 

Part I: Schematic of the circuit to be designed in the HDW-LC4128V board (switches, buttons, LEDs and 7-segment digits)

mult

  1. Specifying a large project and planning the dedicated processor architecture. (pdf1)

    1. Read the old ED Unit 2.13 , The shift -and- add algorithm

    2. Example of hardware multiplier using logic gates and Proteus, 7x7 signed multiplier, Ref. Oscar Vila and D. Valderrama,2007-2008.

    3. Example of a serial multiplier from ED (The  block diagram in Proteus )

  2. The proposed internal architecture (pdf2)

mult_symbol

  1. The 4x4 unsigned multiplier and the proposed datapath (pdf3). Some examples (pdf4)

  2. The 5 seconds timer (pdf5)

  3. The design of the control unit (FSM) (pdf6)

Part II: VHDL simulation  using test benches

  • Here the idea is: firstly, run the demonstration in Unit 3.4; secondly, do a similar simulation with one of your components for the multiplier.

  • Let's start with the test bench for a data register like the one used as working register W in the datapath

 

Part III: Implementing the project: a bottom - up strategy to build every component

 

Number of VHDL files involved Block to be designed Entity name (VHD) Test bench
(template from the ispLEVER tool and modified)
1 The 8-bit parallel data registers with synchronous reset (W and C)
(Unit 2.7)
Data_Reg_8bit.vhd Data_Reg_8bit.vht

 

Number of VHDL files involved Block to be designed Entity name (VHD) Test bench
(template from the ispLEVER tool and modified)
1 The 8 - bit universal shift register (A) (Unit 2.10) Shift_Data_Reg_8bit.vhd Shift_Data_Reg_8bit.vht

 

Here you have the whole project:

Number of VHDL files involved Block to be designed Entity name (VHD) / top design Components (hierarchy level 1) Components Components
20 The structure of the top design multiplier.vhd unsigned_4bit_multiplier.vhd
timer.vhd
Quad_Mux4.vhd
Bin_BCD_converter_8bits.vhd
BCD_7seg.vhd
OSC_FREQ_DIV.vhd
(Check the next table)  

 

And everyone of its components: (The symbol vert means that the file is finished)

Number of VHDL files involved Block to be designed Entity name (VHD) / top design Components (hierarchy level 1) Components (hierarchy level 2) Components (hierarchy level 3)
8 The 4x4 unsigned serial multiplier


(The adder can be adapted from Unit 1.6)
unsigned_4bit_multiplier.vhd vert Datapath.vhd vert
Data_Reg_8bit.vhd  vert

Shift_Data_Reg_8bits.vhd

Shift_Data_Reg_4bits.vhd

 
Adder_8bit.vhd One_bit_adder.vhd vert
control_unit_multiplier.vhd    
3 5 s timer. This is a complex digital system in itself: a datapath, in this case a counter, controlled by a FSM

(adapt the VHDL file from Unit 2.3)
timer.vhd counter.vhd

control_unit_timer.vhd
   
1 4MUX4  (Chapter 1) Quad_MUX4.vhd      
2 Code converter from binary to BCD (Units, tens and Hundreds)
(Chapter 1, see a truth table and a block diagram for the 74185 chip)
Bin_BCD_converter_8bit.vhd Bin_BCD_type74185.vhd    
1 Binary to 7 segment decoder with "H" symbol
(An example of a similar file in Unit 1.9)
BCD_7seg.vhd      
5 Clock divider

(See Chapter 2, EX2 Part II)
OSC_FREQ_DIV.vhd Freq_Div_100.vhd

Freq_Div_50.vhd

Freq_Div_2.vhd

T_Flip_Flop.vhd vert
   

 

  • Here you are an example of the RTL view from the Synplify synthesis tool for the "Unsigned_4bit_multiplier" module, so that you can check each connection with the initial sketch at the pdf3. Once every single component has been verified using a test bench, you can replace or correct its template file from this table and go from the bottom to the top "Multiplier" project.
  • Remember to check also in the Fitter report file number of registers (flip-flops) used per component.

symbol

multiplier

And the Datapath internal structure

datapath

 

Part IV: Adding extra features, for instance using a matrix keyboard for inputting the operands.

 


At this point of the course, you can plan and solve a "research" problem like "Comparing performance of hardware and serial binary multipliers", trying to investigate questions like, which multiplier is faster, which one involves more resources, which one is easy to redesign or readapt to different programmable chips? (In is not the same, but here you can figure out an idea of a similar paper)


At this point of the course, is also very interesting to take a look at some books, in order to realise where are the concepts you've learned since now in a wider picture of the subject of programmable logic devices. We recommend you this introductory book form Xilinx engineers. 


Here you are a brand new set of Lattice demonstration and training boards. Take a look at the software and the hardware specifications. So, realise that after having gone through all this first section of the course on programmable logic, you have gained access to a great deal of specialised knowledge content form Lattice, Altera and Xilinx PLD's and FPGA's.

lattice


NEW NOTE: The ActiveHDL Latice Edition 8.2 is working again. Lattice engineers have solve today May 6 the problem with this simulation suite from Aldec. You have to ask for a new ispLEVER Classic license.

licence

Aldec



Chapter 4 Microcontrollers

boleta EX4A (docx)

Part A: Microcontroller development environment installation and the theory of microcontrollers

  • Install MPLAB (v 8.6) + HI-TECH C Lite Compiler for PIC10/12/16 MCUs (9.7)(which is now included in the MPLAB bundle). Unit 4.5 and Unit 4.6
Microchip                                               MPLAB
Hi-TechHi-Tech C compiler (old SED Unit 2.9)
  • Let's run our first circuit using C language (Unit 4.6) for microcontrollers.
    • Introductory Design example 1: a combinational circuit (Chapter I). An 8-bit binary comparator. 

comp

Part B: Designing a sequential system

  • Design example 2: An 8-bit counter (Chapter II). The FSM-like programming style. Unit 4.9

COUNTER

  • Design example 3: An 1-digit BCD counter (Chapter II). The FSM-like programming style using state enumerations Unit 4.9

One digit

  • Development board  Picdem2 PLUS training board. Read Unit 4.7

/picdem2

  • ==>  Adapt the previous Design example 3 to the Picdem2 PLUS board

 

  • Downloading and debugging the C code : Using the in circuit debugger- programmer ICD2/ICD3. Unit 4.8

 

Part C:  Designing with peripherals: a dedicated processor using the Timer0.  Unit 4.10

 

  • ==>  Adapt the previous Design example 4 to use Picdem2 PLUS board LCD display to notify the game's result. (Unit 4.11)

 


boleta EX4B (docx)

  • ==>  Implement a 5 seconds timer using the Timer 1 peripheral (Unit 4.12)

 



boleta EX4C Application project:

The idea is quite simple: You already know how to implement an application using C, MPLAB, Proteus-VSM, FSM programming style, interrupts, I/O, Timers, LCD and the PICDEM2+ development board to test your final designs. Thus, now, to finish the course, we ask you to enhance anyone of the basic previous applications or a new one that you may have in mind, with another peripheral and write and present the project.

This last assignment is basically a self-directed activity,  where your skills for finding information, clarifying ideas and concepts, organising a plan, and carrying out it accordingly to your own initiative, are going to be determinant,  however, you can still count on our office tutoring time.

  • Here you are an example "docx" template. 
  • Take the "pptx" template from the Library audio/video resources
  • And read other project-related information at AP page
    • Due date for EX4B and the AP is June 22

Other microcontroller peripherals and applications:

  • ==> Data acquisition. The A/D peripheral. Unit 2.13

 


electro