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Chapter I Combinational circuits

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Unit 1.1. Cooperative learning. Why we'll use teamwork to solve problems?

Unit 1.2. Installing Proteus - ISIS

Unit 1.3. Analysis flow: Analysis of a small combinational circuit. From the circuit (realisation) to the truth table (specifications).

Unit 1.4. Using WolframAlpha to analyse a small circuit. Deduce the truth table from the logic diagram or Boolean equations.

Unit 1.5A. Installing Lattice
ispLEVER Classic / Diamond
Unit 1.5B. Installing Altera Quartus II Unit 1.5C. Installing Xilinx ISE

Unit 1.6. Implementation of digital circuits into a sPLD; Gal22V10 structure. VHDL entry files, synthesis, electrical simulation using Proteus-ISIS, implementation and prototyping. The training PROTOGAL board.

Unit 1.7. VHDL basics for combinational circuits. Entity, architecture, signals, components, etc...

Unit 1.8. Using Minilog.exe to minimise logic functions. Simplifying simple gate-based combinational circuits.

Unit 1.9. Design flow  for small combinational circuits. Behavioural  or structural approach. From the specifications to the implementation in a PLD.

Unit 1.10. Design flow for large combinational circuits. Structural top-down (hierarchical) approach and component instantiation.  

Unit 1.11. CPLD and FPGA devices. VHDL design flow: entry files, functional simulation, pin assignment, synthesis, gate level (timing) simulation, implementation and prototyping. 

Unit 1.12 Electrical parameters of classic chips and programmable devices.

Unit 1.13A. Installing ActiveHDL Lattice Edition (Aldec)

Unit 1.13B. Installing ModelSim Altera Starter Edition (Mentor Graphics) Unit 1.13C. Using the Xilinx ISim HDL simulator
Unit 1.14A. Functional simulation of combinational circuits using ActiveHDL Lattice Edition (TCL macros and VHDL test bench)

Unit 1.14B. Functional simulation of combinational circuits using ModelSim Altera Starter Edition (TCL macros and the VHDL test bench) Unit 1.14C. Functional (Behavioural) simulation of combinational circuits using ISim (Xilinx) and VHDL test bench
Unit 1.15A Gate-level simulation of combinational circuits using ActiveHDL Lattice Edition (TCL macros and VHDL test bench)

Unit 1.15B. Gate-level simulation of combinational circuits using ModelSim Altera Edition (TCL macros and VHDL test bench) Unit 1.15C. Gate-level simulation of combinational circuits using lSim (Xilinx) and VHDL test bench

 

Unit 1.16. Training and prototyping boards for small CPLD /FPGA