UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

 

Design Circuit_PQ using plan C2 

Circuit_P, Circuit_Q plan A

Circuit_PQ plan B
MoD MoM with MUX_4 and MUX_8 MoM with MUX_2 and MUX_16
1. Specifications Planning Developing Testing Report Prototype

Implement the truth table written in Fig. 1 using a plan C2 architecture based on the method of decoders (MoD) proposed in L3.3.

Circuit_PQ

Fig. 1. Circuit_PQ to desing.

 

Specifications 2. Planning Developing Testing Report Prototype

Fig. 2 shows how to invent the internal architecture based on MoD. Four inputs means using a Dec_4_16 component.

 

Fig. 2. Circuit_PQ schematic using MoD.

We can use other tutorials to find how to implement the internal architecture of the required component Dec_4_16. As usual we can implenent it using several plans.

 

Fig. 3. Designing a Dec_4_16 using Dec_2_4 smaller components of the same kind also clarifies the idea of circuit expandability.

As the last step, let us imagine the component Dec_2_4 using plan B as shown in Fig. 4.

 

Fig. 4. Creating Dec_2_4 using plan B.

In this way, this project will require three VHDL files: Circuit_K.vhd, Dec_4_16.vhd and Dec_2_4.vhd.

Testing the circuit will require the same testbench stimulus process used in Circuit_P_tb.vhd.

The project location may be:

C:\CSD\P3\Circuit_PQ\MoD\(files)

 

Specifications Planning 3. Developing Testing Report Prototype

Translating the schematic into VHDL generates the following files: Circuit_PQ.vhd, Dec_4_16.vhd, Dec_2_4.vhd.

Fig. 5. Circuit_PQ RTL view.

 

Specifications Planning Developing 4. Testing Report Prototype

Using the same testbech stimulus process and Min_Pulse from P1 Circuit_Q tutorial Circuit PQ_tb.vhd, we can verify our complete hierarchical structure as shown in Fig. 6.

 

Fig. 1. Circuit_PQ to desing. P = f(S1, S0, A, B), Q = g(S1, S0, A, B)

 

Specifications Planning Developing Testing 5. Report Prototype

Follow this rubric for writing reports.

 

Specifications Planning Developing Testing Report 6. Prototype

We can use the DE10-Lite board to implement this project, as shown in Lab 1.2 for the similar Circuit_W.

 

MoD MoM with MUX_4 and MUX_8 MoM with MUX_2 and MUX_16
1. Specifications Planning Developing Testing Report Prototype

Implement the truth table written in Fig. 1 using a plan C2 architecture based on the method of multiplexers and a MUX_4 as proposed in L3.3.

Circuit_PQ

Fig. 1. Circuit_PQ to desing.

 

Specifications 2. Planning Developing Testing Report Prototype

The project location may be:

C:\CSD\P2\Circuit_K_MoM_A\(files)

 

Specifications Planning 3. Developing Testing Report Prototype

 

 

Specifications Planning Developing 4. Testing Report Prototype

 

 

Specifications Planning Developing Testing 5. Report Prototype

Follow this rubric for writing reports.

 

Specifications Planning Developing Testing Report 6. Prototype

We can use the DE10-Lite board to implement this project, as shown in Lab 1.2 for the similar Circuit_W.

 

MoD MoM with MUX_4 and MUX_8 MoM with MUX_2 and MUX_16
1. Specifications Planning Developing Testing Report Prototype

Implement the truth table written in Fig. 1 using a plan C2 architecture based on the method of multiplexers and a MUX_4 as proposed in L3.3.

Circuit_PQ

Fig. 1. Circuit_PQ to desing.

 

Specifications 2. Planning Developing Testing Report Prototype

The project location may be:

C:\CSD\P2\Circuit_PQ_MoM_B\(files)

 

Specifications Planning 3. Developing Testing Report Prototype

 

 

Specifications Planning Developing 4. Testing Report Prototype

 

 

Specifications Planning Developing Testing 5. Report Prototype

Follow this rubric for writing reports.

 

Specifications Planning Developing Testing Report 6. Prototype

We can use the DE10-Lite board to implement this project, as shown in Lab 1.2 for the similar Circuit_W.