UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

      - D2.9 -

Water tank controller (FPGA-VHDL)

Products

D2.8

D2.10

1. Specifications

We want to design a water tank controller (Water_tank_controller) as an FSM that can drive two pumps independently, as represented in Fig. 1. The tank has level sensors D1, D2, and D3 attached to the wall, so that a '1' is generated when the sensor is sunk into water. The controller works as follows: when the tank is empty, below D1, both pumps work simultaneously; when the water level is above D2 pump P1 stops; when the water is above D3, meaning that the tank is full, pump P2 stops; and finally, the pumps do not switch on until the water level is again below D1.

The same project designed programming a μC is in D3.9.

Water tank

Fig. 1. Diagram of the water tank installation.

What power driving circuits can be used to control the two 300W 220VAC/50Hz pumps?

In addition to controlling the water level in the tank, we also want to indicate in a LED column and using a 7-segment digit the current level of the water in the tank.

The user wanted to add an extra circuit to translate the LED column code into a 7-segment display. Thus, an additional combinational circuit CC3 is required to meet this new specification. Let us solve the problem using the ROM method for implementing logic functions. The wiring in Fig. 2 shows the naming conventions for the vector HEX0_L(6..0) common anode in the DE2-115 board user guide page 36 (or the DE10-Lite). Discuss the size [2^m x n] of the ROM and add this circuit to your system. 

7-segment display

Fig. 2. Enhancement with a 7-segment display.

In a new design phase we will include a real-time clock to measure how long does it take to empty the tank once full and the tap turns on.

 

2. Planning

Design phase #1: basic features: FSM

Solve the circuit for the design step #1. Only when it is fully tested working correctly and reported, solve the design step #2.

- Design step #1. Consider an initial circuit only with the sensors, the pump outputs and the 4-LED column.

- Design step #2. Add the 7-segment

Design phase #2: advanced features to measure how long does it takes to empty the tank.

- Design step #1: Design a CLK generator to obtain all the necessary CLK signals from the target board quartz crystal oscillator. Deduce the number of D_FF required for this subcircuit.

 

- Design step #2. Build the datapath. Design a real-time clock for minuts, seconds and tenths of a second (MM:SS:T) that can start and stop using a button.

- Design step #2. Implement the dedicated processor. Connect the chronometer to the system, so that the clock starts when water flow is detected in the drain tap and stops when the empty signal D1 is detected. What kind of sensors can be used to detect water flow?

 

For solving  the step #1 of the design phase #1, we will apply systematically the FSM architecture to this problem.

Fig 3 shows the Water_tank_controller symbol and details.

tank and symbol

Fig. 3. Tank sketch and symbol. CLK oscillator is 125 kHz.

Draw the state diagram. Fig. 4 shows an example.

State diagram

Fig. 4. State diagram example.

Adapt the FSM architecture to this problem, naming and connecting all signals and inputs and outputs. This will be translated as a single plan C1 VHDL file.

Sketch a timing diagram showing the main operations and also imagining states.

Deduce how many D_FF are required when encoding FSM states using the following options and draw the state register memory:

Option #1: radix-2 (sequential)

Option #2: Gray

Option #3: Johnson

Option #4: one-hot

Write the CC2 truth table to obtain the outputs of the circuit and its flowchart.

Design the CC1 truth table to obtain the next state to go and its flowchart.

Write the VHDL file

Start a Quartus Prime synthesis project for one of the following programmable target chips:

Option #1: Cyclone IV EP4CE115F29C7

Option #2: MAX II EPM2210F324C3

Option #3: MAX 10 10M50DAF484C7 (for gate-level simulations, choose one of the previous options)

Inspect and discuss the RTL and technology schematics. Check the number of D_FF.

Draw the testbench fixture, write a VHDL stimulus and run the EDA simulation tool to verify your design. Measure the maximum CLK frequency that can be applied to your design considering your target chip.