upc eetac_1

Project P1 on Designing circuits using logic gates


Circuit_1

1.Specifications

Section A.- Draw the symbol and deduce a truth table of the following circuits:  Circuit_1C  - Circuit_1D

C = f (D1, D0, A, B)               D = g (D1, D0, A, B)

Section B.- Synthesise two or three different circuits using gates that comply with the truth table found above:

1.- Using canonical equations (maxterms or minterns)

2.- Using the minimised equations from minilog.exe (a Karnaugh map computer application) C= SoP; D = PoS

3.- Using any kind of logic equations. For instance Circuit J with only NOR gates, Circuit K with only-NAND gates

To implement the different designs use software like:

Proteus ISIS virtual laboratory simulator (tutorial).

WolframAlpha computation engine (tutorial).

Minilog.exe application to simplify truth tables (the former Unit 1.8 tutorial).

 

Learning materials:

Digital

2. Planning

Let's do the same exercise using three different approaches and compare solutions.

1. Let's solve completely the Circuit_1C, and then, (if you have time left),

2. repeat all if necessary for the Circuit_1D.

Do not do both circuits at the same time. Here you are an example of a plan. So firstly, let's obtain the truth table using different ways and software tools. Remember that this truth table obtained in Section A) must be verified (with other students, with different tools, etc.) before to proceed with Section B). Once you have the truth table, you can develop/invent/create/infer and test several circuits like:

1.- Use the canonical equations (maxterms or minterms) --> Circuit 1

2.- Use SoP or PoS  -->  Circuit_2 (minilog to simplify the truth table)

3.- Once you have demonstrated and validated the Circuit_2, using Proteus for instance, you can transform the algebraic equation so that only only-NOR is required to draw a circuit (--> Circuit_3).

4.- Etc.

 

3. Development

Development (the way to proceed and the necessary CAD/EDA tools will depend on the plan). For example:

1.- Draw/capture  the circuit schematic in Proteus and run a simulation.

2.- Analytical method using Boole's Algebra or Minilog.exe to deduce simpler equations.

3.- Write the circuit equations in WolframAlpha and run the engine to obtain truth tables (remember that they have to be interpreted correctly). 

4.- Use VHDL synthesis and simulation to obtain circuits and truth tables (in P2).

 

4. Testing

The same applies to testing. There are several ways to test that the truth table or the circuit that you have invented works as expected.

1.- Test the circuit in Proteus to obtain the truth table applying all the combinations consecutively.

2.- Run the WolframAlpha numerical engine to obtain the truth table inspecting and interpreting the program's outputs.

3.- Write the circuit equations or truth table in VHDL, synthesise the circuit and test it using a VHDL simulator (testbench and timing diagram to compare the truth table) [Let's do it once and again like this in the next projects].

 

5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources

 

6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works

 

Other similar projects

- In addition to the three methods discussed in this P1 project to obtain the truth table of a simple combinational circuit, there is another one which uses VHDL synthesis and simulation tools. See the example here in this tutorial.

Other materials of interest

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