Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC - UPC
upc eetac_1

Project P3 on arithmetic circuits: addition and subtraction in two's complement (2C)


8-bit binary adder  (standard chips 74HCT283, 74LS182)

1. Specifications

Addder_8bit

Fig. 1. Symbol of an 8-bit binary adder. (Visio)

Learning materials:

- Let's learn how to perform basic operations using the binary number system: addition, subtraction, comparison, multiplication, etc. Subtraction and other operations using integers (in two's complement) are scheduled in  P4.

- Tutorial on how to design a 1-bit adder using both, structural equations and behavioural approaches (flat designs, single file project).

- Tutorial on how to design a 4-bit adder based on ripple carry technique, a component like the standard 74HCT283 using a structural hierarchical  (multiple VHDL files approach). It can be used as a seed project to copy and adapt to any other large design.

- Tutorial on how to build a MUX8 using a structural hierarchical  (multiple VHDL files approach). This is the C2 method pointed in P2, and can be used as a seed project to copy and adapt to any other large design.

- How does the method of decoders for implementing logic functions work? Class notes (1), (more stuff on decoders).

- How does  the method of multiplexers for implementing logic functions work? Class notes (1), (more stuff on multiplexers).

PRINT convenient documents from these tutorial exercises and use them to discuss the projects. 

NOTE: This unit is orientative and tell you about building adders. It is like a tutorial to better organise your work, and so, you must adapt its content to the proposed exercices in class (blog).

2. Planning

Even though, as in the previous projects, we have the two possibilities, structural and behavioural, let's design this P3 structurally using COMPONENTS and SIGNALS; therefore as a multiple VHDL file project. Learning how to use components is the key point of the CSD course because it'll allow you to plan very large and complicated circuits hierarchically, as you saw in the Proteus schematics, where you can go "Cntl+C" to the child sheet of each entity subcircuit. Thus, from now on, the subcircuits will become components.

This is the general layout.

Project Adder_1bit:

Project A: Let's design an Adder_1bit using the method of multiplexers.

<disk>/CSD/P3/PA/(files)

How many VHDL files are required? Name them all.

You can use this method of implementing truth tables to design any kind of combinational circuit. For instance, try the design of the Circuit_C in P1).

 

Project B: Let's design an Adder_1bit using the method of decoders.

<disk>/CSD/P3/PB/(files)

How many VHDL files are required? Name them all.

You can use this method of implementing truth tables to design any kind of combinational circuit. For instance, try the design of the Circuit_C in P1).


Project Adder_4bit:

Plan 1: This is a ripple carry Adder_4bit (tutorial).  The Adder_1bit component can contain any architecture (the equations-based in this tutorial, or the Project A or the Project B above).

Plan 2: Let's build a 4-bit carry-lookahead adder. So, both the ripple carry and the carry-lookahead adders have the same block and entity definition, but different internal architectures. And so, they will have different performance when implemented in a CPLD chip.

<disk>/CSD/P3/lookahead/(files)

Adder_4bit

Adder_4bit

Fig. 2. The idea of the carry-lookahead to reduce the propagation time in the addition operation. Source: Wikipedia, and this book: Ercegovac, M., Lang, T., Moreno, J. H., "Introduction to Digital Systems", John Wiley & Sons, 1999), which also includes high quality slides. Chapter 10 is on arithmetic circuits. Here you'll find the set of equations that define the Carry_generator component.

 

https://upload.wikimedia.org/wikipedia/commons/thumb/0/04/4-bit_carry_lookahead_adder.svg/250px-4-bit_carry_lookahead_adder.svg.png

Thus, this in Fig. 3 is the proposed plan for the circuit. How many VHDL files are required? Name them all.

CLA

Fig. 3. The plan to design the 4-bit carry-lookahead adder with the structural internal architecture of the component Carry_generator and its equations for obtaining all the carries with only 3-levels-of-gates.


Project Adder_8bit:

Structural design:

- Draw the sketch of this hierarchical project (class discussion).

- Count and name all the VHDL file involved in the project. Name the folder to keep all the project files as follows:

<disk>/CSD/P3/Adder_8bit/(files)


Organise the work in cooperative groups to be able to handle that set of projects, keeping the weekly workload under control while everybody learn everything. 

 

3. Development

We have to run 4 projects in the usual way: writing the schematics in VHDL. Indeed, you can use always this Adder_4bit.vhd (or this MUX8.vhd) to adapt any project from now on. Run the EDA tool to synthesise the circuit. Print and comment the RTL  schematic.

1. Run the project PA Adder_1bit using the method of multiplexers and discuss the RTL. Print also the technology view and identify components.

2. Run the project PB Adder_1bit using the method of decoders and discuss the RTL. Print also the technology view and identify components.

3. Write the code of the project Adder_4bit based on carry look-ahead techniques, from the previous schematics and diagrams, run the EDA tools and check how it looks like when synthesised using the RTL view.

4. Once you have completed the steps 1) and 3), you can start the development of the Adder_8bit.vhd. Write down the VHDL files using components and signals.

 

4. Testing

Testing goes attached to each project once developed.  

To convert the initial timing diagram sketch into a VHDL testbench Adder_8bit.vht (or Adder_8bit_tb.vhd) write the inputs activity (start with only a few vectors) and the Min_Pulse constant in the template produced by the EDA tool. Surely, it's going to be a good idea the adaptation of the test vectors performed on the 4-bit adder ripple carry already available as a tutorial.

NOTE for ModelSim Altera Edition: Remember that you have to change the  colour scheme of the EDA tool to replace the black background by a white one.

Run the EDA VHDL simulator and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms.

 

5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources.

The idea of a report at this level has to be clear for you now: technical document that demonstrates the way you have designed a given product. Furthermore, it allows you to prepare an oral presentation because it includes everything to generate high quality slides. Simple class notes and conventional exercices may be right for passing exams, but using your project reports you'll be able to teach your peers as if you had become a class instructor.

(Optional) You can think in organising your ePortfolio accordingly to this template and instructions. Scan your pen-and-paper project reports using our EETAC printers and send the pdf files to your email account.

 

6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.

 

Other similar projects on arithmetic combinational circuits

- Here you are a similar project in Proteus, the 8-bit adder and subtractor that will be used in P4. Run it and visualise how the input and output operands looks like.

- Here you are many HADES Java applets on arithmetic circuits.

- This is an example of a 7-bit signed multiplier build using a network of cascadable 1-bit multipliers and other logic circuits. 

- Comparators, number of ones counter, etc.

Other materials of interest

- - There are several former units and exercises on arithmetic circuits (1), (2), as well as hundreds of web pages and videos over the internet. Every book on the subject has several chapters on arithmetic circuits because they are fundamental blocks of computers.

- The list of projects proposed in the P3 to study basic standard arithmetic circuits.