upc eetac_1

Project P4 on large (hierarchical) combinational circuits

 Arithmetic and logic units, gate-level simulation

8-bit binary adder  and subtractor (ALU type 74181)

1. Specifications

Solve basic arithmetic operations for integer numbers (add, subtract, compare, multiply, etc.).

1.- Design an 8-bit adder/subtractor in two's complement with zero(Z), carry (C) and overflow (OV) flags using VHDL and a multiple file hierarchical structural approach. 

Discus the symbol (below in Fig 1) , the truth table and the timing diagram of this circuit. How long is the truth table?


Fig. 1. Symbol of an 8-bit 2C  adder/subtractor.

2.- After the circuit works and is tested as usual, perform a a gate-level simulation to determine the circuit maximum speed of operation. Measure the circuit's speed using both: (a) ripple carry Adder_4bit and (b) carry lookahead, as well as different implementations of the Adder_1bit.

Thus, this may be the P4 organisation.

Learning materials:

- Let's learn how to perform basic operations using binary number system: addition, subtraction, comparison, multiplication, etc. Explain how does work the two's complement (2C) to represent positive and negative integer numbers. Solve exercises on arithmetic operations (like in the problem 1.4.2 in this collection). 

- Tutorial on how to design an 4-bit ones counter using a hierarchical structural approach based on implementing logic functions using the method of decoders. This tutorial includes also a gate-level simulation example to determine the maximum speed of operation of the synthesised circuit into the CPLD/FPGA.

- Tutorial on how to design an 8-bit ones counter using a hierarchical structural approach cascading simpler components of the same kind. This tutorial includes also a gate-level simulation example to determine the maximum speed of operation of the synthesised circuit into the CPLD/FPGA.

- Tutorial on gate-level simulations: former unit 1.15A (Lattice), 1.15B (Altera), 1.15C (Xilinx).


2. Planning

- Structural design. Thus, as you've seen in P3, let's plan the following problems:

Design flow steps: 1) - 2) - 3) - 4)

Theory: perform several example operations (using both positive and negative numbers) on the circuit  that you have invented to verify whether your circuit works as expected or not. Be aware of the zero (Z), overflow (OV), and carry (C) situations. For instance, repeat the P3-PC hierarchical design procedure to translate your top entity project to VHDL. 

Design the structure of an 8-bit adder/subtractor using components and signals as it is in this class discussion. Use any hierarchical example or tutorial project to copy and adapt and get the components from previous projects. Study how the overflow logic (OV) works and why it is designed so (these are old class-notes on how to obtain the OV output [1], [2]and [3]).

- Count and name all the VHDL files involved in the project. Name the folder to keep all the project files: 


Implement the project as planned

Test the project functionally 


5) Add the gate-level simulation as the last step in the design flow. So that you can perform measurements of the circuits' speed (millions of operations per second (Mops)


3. Development

Once you have completed the steps 1), 2) and 3), you can start the development of the Adder_subtractor_8bit.vhd. Write down the VHDL files using components and signals modifying a convenient seed circuit.

Run the EDA tool to synthesise the circuit.  

Print and comment the RTL  schematic. Is it like what you had sketched in the plan?


4. Testing (functional simulation)

From the initial timing diagram sketch:

Functional simulation. Convert the timing diagram sketch into a VHDL testbench Adder_subtractor_8bit.vht (or Adder_subtractor_8bit_tb.vhd) writing the inputs activity and the Min_Pulse constant in the template produced by the EDA tool. Surely, it's going to be a good idea the adaptation of the test vectors performed on the 8-bit adder. Use positive and negative numbers.

 Run the EDA VHDL simulator and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms.


5. Testing (gate-level simulation)

Run a gate-level simulation to measure the worst case delay and the maximum speed of operation (or highest computation speed) of the synthesised circuit.

Make a simulation to show that the circuit cannot produce correct results when the Min_Pulse constant is less that the worst case delay.  


6. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx, pptx, or any other resources. Take care of the computer folders where the project are archived. 


7. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.


Other similar projects on arithmetic combinational circuits

- Here you are a similar project in Proteus: 8-bit adder and subtractor. Run and try it to visualise better how it operates the input and output data.

- Here you are many HADES Java applets on arithmetic circuits.

- This is an example of a 7-bit signed multiplier build using a network of cascadable 1-bit multipliers and other logic circuits. 

- Comparators, parity generators, multipliers, etc.


Other materials of interest

- There are several former units and exercises on arithmetic circuits (1), (2), as well as hundreds of web pages and videos over the internet. Every book on the subject has several chapters on arithmetic circuits because they are fundamental blocks of computers.

Dedicated processor

Fig. 2. A dedicated processor representing the Arithmetic and Logic Unit (ALU) as the core of the datapath structure. Source: Hwang, E., Digital Logic and Microprocessor Design with VHDL, CL-Engineering, 2005.

- This is an example exercise IT1 (pdf) that contains many concepts develop since now through P1 .. P4. This is the Proteus file, the truth table in Minilog and the results when simplifying by PoS. This is the discussion on the problem solved some years ago.

- This is another similar exercise  IT1r (pdf). The truth table, the Minilog result, and the symbol in Proteus that can be simulated attaching this "jed" to the AM22V10 sPLD. This is a possible VHDL file (question 5), and this is the ispLEVER Classic report where you see the pin connections after synthesising the circuit.