upc eetac_1

Project P8 on a keypad-controlled  timer


CLK generators and hardware dedicated processors

1. Specifications

Let's connect P6 and P7 together to generate a keypad-controlled programmable timer. At the same time we'll develop some ideas on the CLK generator component to derive all the CLK signals from the same crystal oscillator.

This project, as the last one in this Chapter II, is going to be solved more autonomously. You have to try to organise the general architecture of the Timer_keypad block in Fig. 1 to command the Programmable_timer from P7 and the matrix_encoder_16key_registered circuit from P6 (Part #2).

Schematic

Fig 1. Symbol and electrical schematic for the proposed keypad-controlled programmable timer.

System specifications:

- Teamwork, project and time management, English.

- Solve the CLK_Generator chip to generate 100 kHz (SCLK), 200 Hz (MCLK) and the time base signal of 1 Hz from the crystal quartz oscillator available in the training board. For instance, the 25.175 MHz in the Altera's UP2 or the 50 MHz from the Digilent NESYS 2 board or the 1 MHz CLK signal in the HWD-LC4128V from Lattice Semiconductor. 

- Organise the system architecture to read to read the T1 time from the keypad (maximum time is 99 s) , and trigger the timer when clicking the key '*' (or 'F') . The key 'C' the system reset.

- Extra: the ready green LED can be set in intermittent mode at 2 Hz rate when timing.

- Extra: when the timing period ends, generate a 10 s audible sound (square wave of about 1.5 kHz).

- Etc., fir example replacing this local keypad by a computer connected using a RS232 USARTor a I2C bus to the programmable timer.  

 

Learning materials

Learning materials and tutorials on how to design large frequency dividers: 

- On the design of a large synchronous frequency divider with many pulsed and squared outputs generated from a high frequency crystal quartz oscillator. Here you are the bicycle LED torch (P6) with its internal CLK_Generator circuit.

- Study other similar dedicated processors to comprehend how a dedicated processor architecture can be applied once and again in a very diversified set of applications based on hardware design. Naturally, many of these application can be redesigned using a software-based microcontroller. P9 is the introduction to this device.

 

2. Planning (Devising a strategy to solve the problem)

Organise the hierarchical architecture discussed in class and represented in Fig. 2. This large project must be solved in several steps using teamwork.

plan

Fig. 2. Schematic discussed in class (zoom to view). Discuss which section of the circuit may be the datapath,  and which wires may be status signals, control inputs and outputs, and data inputs and outputs. Is there a circuit that can be considered a peripheral?. A dedicated processor diagram and conceptions.

1) Chip 6. Plan the CLK_generator.vhd. Explain how it works and the signals generated, adapting it to your own board. This is for instance and example of internal architecture when using an Altera UP2 board, therefore, adapt it to our especifications. 

 

Fig. 3. Plan for building a CLK generator, which is basically a frequency divider from the crystal oscillator OSC_CLK_in.

2) Chip 4. Design the combinational circuit BCD_BIN_converter_2dig (symbol) used for translating the BCD keypad codes to a binary number, thus it can be understood by the programmable timer. In this application the maximum value that can be programmed is 99 s which generates the  corresponding 7-bit number "1100011".

Because this is the last project in hardware design, it is a good idea to show you the power of VHDL synthesising algorithms in hardware. Here you are the discussion of 2 proposed plans. Plan A is structural as it was learnt in P3. Plan B is behavioural, showing you how from the tutorial demonstration examples adder and multiplier, we can organise the schematic, write the code VHDL, inspect the RTL (in Fig. 4), the technology and test it functionally or at the gate-level using for example this test bench.

RTL

Fig. 4. RTL view of the converter's equation.

3) Chip 1. Finish the P6 Part #2 to obtain the matrix_encoder_16key_registered. Indications on how to proceed are incorporated in P6.

 

4) Find the VHDL code for the data registers and discuss which may be a state diagram for the Chip 7 Control_FSM that will handle it all. 

 

5) Mount the top circuit assembling all the components into a single project: programmable_timer (P7), matrix_encoder_16key_registered (P6), CLK_generator, Control_Unit_FSM, etc. This is translating the general sketch to VHDL and be able to inspect the RTL view, even if yet some architectures are not finished. The folder of the project:

<hard drive>/CSD/P8/(files)

 

NOTE: Running ispLEVER Classic with the architecture of some components missing generates an error. But you still can open Synplify Pro to get the RTL view. The application shows in yellow the entities which includes the architecture and in white the components yet to be designed. 

 

3. Developing

This is an example file which can be in this problem:  a freq_div_25.vhd. Modify it conveniently to generate other similar components. Thus, organise the complete CLK_Generator using frequency dividers and toggle flip-flops (T-FF)to square the pulsed waveforms.

While examining the EDA results, the RTL schematic, be aware of the number of registers (DFF) used in the target chip and justify the value.  Does it match with your initial estimation?

And so on ...

 

4. Testing 

Complete the template test bench file and run the EDA tool.

 

5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources .

Remember that in class you'll be required to explain any section of your project individually or in group.

 

6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.

 

Other similar projects on sequential circuits

Here you are some examples of former complete projects involving many VHDL files in a similar hierarchical architecture. The same robust and clear design procedures has been applied once and again gaining reliability and know-how:

- Serial adder (ref.)

- Serial multiplier (ref.)

- USART subsystem to transmit and receive asynchronous data (ref.)

- This is a final project on a traffic light controller.

 

Other materials of interest

 Up to this point in the course, you've learned what represents the basics of hardware design of modern digital systems. No doubt that you can continue this subject's content going on further on the design of more advanced systems and even microprocessors and microcontrollers. However, the chapter 3 of this introductory CSD course will be based on the use of a commercial microcontroller precisely to repeat some previous project but from the software point of view.