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P_Ch2 - Project P8 on a keypad-controlled  timer


CLK generators and hardware dedicated processors

1. Specifications

Let's connect components developed using P6 and P7 techniques to generate a timer circuit that can count down up to one hour real-time (Timer_MMSS). At the same time we'll develop some ideas on the CLK_generator component to derive all the CLK signals from the same external quartz crystal oscillator.

This project, as the last one in this Chapter II, is going to be solved more autonomously. You have to try to organise the general architecture of the Timer_MMSS in Fig. 1.


Fig 1. Symbol and electrical schematic for the proposed timer.  

System specifications:

- Teamwork, project and time management, English.

- Specifications for the Xilinx Nexys 2 FPGA Board  or the Altera terasic DE0 Board board.

- This is the project solved in Proteus for demonstration purposes (unzip both files in the same folder and run the simulation).


Learning materials

Learning materials and tutorials on how to design large frequency dividers: 

- On the design of a large synchronous frequency divider with many pulsed and squared outputs generated from a high frequency crystal quartz oscillator. Here you are the bicycle LED torch (P6) with its internal CLK_Generator circuit.

- Study other similar dedicated processors to comprehend how a dedicated processor architecture can be applied once and again in a very diversified set of applications based on hardware design. Naturally, many of these application can be redesigned using a software-based microcontroller. P9 is the introduction to this device.


2. Planning (Devising a strategy to solve the problem)

Organise the hierarchical architecture discussed in class and represented in Fig. 2. This large project must be solved in several steps using teamwork.

- This is the idea of the dedicated processor


Fig. 2. General plan.

- This is the idea of the datapath.  This is the component BCD_Counter_mod60  (visio), which can be used twice for implementing the Counter_MMSS for counting seconds and minutes. 

- This is the idea of the control unit

- This is how you can divide the CLK frequency by a given number N and how to square the signal using a T-FF. And this is the idea of the complete CLK_generator circuit.  For instance to be used in an Altera DE0 board that includes a 50 MHz oscillator.

DE0 oscillator

Fig. 3.  Altera DE0 board 50 MHz oscillator, from which we'll derive  synchronous squared CLK signals of: 100 kHz, 1.6 kHz, 20 Hz, and 1 Hz.


3. Developing

Better to start with the CLK_generator,  then with the Datapath, and finally with the Control_unit in order to assemble it all as the Timer_MMSS.

This is an example file which can be in this problem:  a freq_div_25.vhd. Modify it conveniently to generate other similar components. Thus, organise the complete CLK_Generator using frequency dividers and toggle flip-flops (T-Flip_Flop)to square the pulsed waveforms.

While examining the EDA results, the RTL schematic, be aware of the number of registers (DFF) used in the target chip and justify the value. Does it match with your initial estimation?

And so on ...


Fig. 3. RTL view of the CLK generator.


4. Testing 

Complete the template test bench file and run the EDA tool.

For instance, in case of simulationg the CLK_Generator alone, as a component, you can speed up the simulatiuon tricking the frequency dividers while keeping the number of registers used and everything else, as shown in Fig. 4. The output waveforms will be of different frequencies, but they will be synchronous and identical as in the real CLK_Generator.

Fig. 4. Modification in the VHDL code to speed up the simulations of the CLK_Generator component. 

5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources .

Remember that in class you'll be required to explain any section of your project individually or in group.


6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.


Other similar projects on sequential circuits

Here you are some examples of former complete projects involving many VHDL files in a similar hierarchical architecture. The same robust and clear design procedures has been applied once and again gaining reliability and know-how:

- Serial adder (ref.)

- Serial multiplier (ref.)

- USART subsystem to transmit and receive asynchronous data (ref.)

- This is a final project on a traffic light controller.

- This is the planning of a programmable timer.

- This is the planning of a programmable timer controlled using a keypad.


- Exams, questions, problems and projects.  This is the P_Ch2 proposed organization and assessment checklist.


Other materials of interest

 Up to this point in the course, you've learned what represents the basics of hardware design of modern digital systems. No doubt that you can continue this subject's content designing with hardware tools and VHDL more advanced systems and even microprocessors and microcontrollers. However, the chapter 3 of this introductory CSD course will be based on the use of a commercial microcontroller precisely to repeat some previous project but from the software point of view.