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P5

Project P6 on finite state machines (FSM)

P7


16-key matrix keypad encoder type MM74C922

1. Specifications

In the first stage of project designing, customers and company staff meet together to discuss which are the features of the product or project under design. We do it in class investing all the necessary time to fully understand how does the system work. 

Symbol

Fig 1. Symbol (Visio)of the Matrix_encoder_16key to be designed using a FSM architecture.

Some theory on how a matrix keyboard operates. In this Proteus simulation there is a 16-key matrix keyboard component. 200 Hz CLK may be a convenient frequency for scanning keys (MM74C922 using a  COSC = 330 nF). 

keyboard freq
  Fig 2. Study and adaptation of the MM74C922 and how the scanning frequency can be fixed for this chip when using its internal oscillator.

 

Learning materials:

Prior to attempting the design of the matrix encoder proposed here, run several of the following tutorials to get in touch with the concepts associated to the FSM architecture:

- Tutorial on the design of the classroom Light control.

- Tutorial: on the design of a LED bicycle torch.

- Tutorial: designing a push button digital low-pass filter and synchroniser.

- Tutorial on the design of a traffic light controller.

- Tutorial design of a binary synchronous counter of a few number of states (Plan X: FSM strategy, state enumeration)

2. Planning

Devising a strategy to solve the problem. This is the engineer's job and the most difficult task. Generally, many teams intervene planning top-down strategies to conceive how the modules can be assembled and interconnected. As you have seen in the many projects solved hitherto, our plan must be a detailed "camera-ready" schematic for a VHDL tranlation.

Before starting this project run at least a tutorial like the LED bicycle torch or the light control system referenced above to see a FSM in action. these tutorial projects will be the theory from whcih to copy & adapt.

Planning ideas

Fig 3. Architecture of the 16-key matrix keyboard encoder FSM and some other planning ideas (click to zoom).

Complete the state diagram and the truth table for the CC2 circuit.

 

3. Development

Carrying out the plan, which usually is the job of an engineer or a technician.

Here we have to write the previous schematics and truth tables in a single VHDL source file like this one based on our CSD style and synthesise a circuit from it using an EDA tool, for instance: 1) Synopsys Synplify Pro Lattice Edition included in ispLEVER Classic, 2) ISE's Xilinx Synthesis Technology (XST), or 3) Mentor Precision RTL included in the Altera Quartus II.  

In our project the RTL view (or the technology view in a lower level), must show the main details of the FSM. Print and comment the schematic indicating the main components CC1, CC2 and the state register. 

This is an example of state diagram as drawn by Synplify Pro Lattice edition that can be inspected in the RTL view. And this is the default encoding (onehot), which means that 8 D_FF are required. Below in Fig. 4 is the technology view of the circuit being synthesised, which give you an idea of the design complexity and resources (instances) used. Count and check that the number of registers D_FF is what is expected. 

tech view

Fig 4. Example of a technology view (click to zoom).

 

4. Testing

Examining test results, engineers must look back to see whether the device comply with the specifications; and forward to see which modifications may achieve better performance. Engineers must be able to organise test procedures to verify that the system works as expected before the next prototyping stage in the laboratory. 

  1. Perform a functional simulation to verify that the device operates like expected in the initial timing diagram sketch.  This is an example testbench file that can be used directly to obtain the results in Fig. 5 or even better, modify it to include other inputs.

Test Example
  Fig 5. Functional simulation with annotations and discussion to determine whether the circuit works as expected. 
  1. Perform a gate level simulation to measure the tCO parameter for a given technology, for instance the Lattice  ispMACH4128V CPLD or the Xilinx Spartan-3E XC3S500E-FG320. Select a conveninet CLK rising edge transition and measure how long does it take to have stable outputs. Which is the maximum processing speed of this circuit? A question equivalent to asking how fast can be scanning and encoding the keypad (in case of not having parasitic effects and key bouncing problems)?

 
  Fig 6. Example of gate level simulations at a given CLK transition. The timing analyser tool can be used to measure the maximum speed of the system CLK:
  fmax = 1/tP
tP   = tCO (the D_FF of the state register) + tPCC (CC2)

Here, if you want to go further, we take advantage of the easiness in using EDA tools. For instance, we can compare circuit realisations and answer questions such:

1) which circuit is faster, the one using onehot or the one using a sequential-binary encoding?

2) which circuit uses more resources? Such answer can be deduced inspecting the timing analyser results.

 

5. Report

By now, you know very well how document your project and what is assessed. Therefore, try to self-assess your project using the rubric discussed in class. It's interesting to look back and annotate remarkable questions that were raised while working on the projects (thanks to students deep engagement and discussion), that in the end can be used to generate a higher quality device (advanced project):

- Why the system gets stuck when the matrix CLK frequency is too high?
- What can be done to prevent the hanging of the system and how it can recover automatically to a known state?
- Which is the advantage of using deboucing filters in each column?
- What can be done to design a system with all the outputs fully synchronised?
- What can be done to read/sample the columns on the rising edge of the CLK, so that they are going to be kept freezed until the next rising edge?

 

6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.

It is interesting in order to see how the circuit works, to use some extra LED to visualise signals and data, which implies building a top schematic containing for instance a HEX_7SEG_DECODER to represent the 16 hexadecimal symbols. This is the top schematic to be implemented in the HWDLC4128V board (schematic) populated with a ispMACH4128V CPLD from Lattice Semiconductor. And this is the RTL view interpreted by Synplify Pro synthesiser tool.

Symbol TOP

Fig 7. The top schematic symbol that includes some extra ports for debugging purposes generated by the ispLEVER Classic. This is the complete zipped project where you can examine the top VHDL file.

Once the development board has been chosen, we have to assign PLD pins to inputs and outputs. This task is conveniently done using the spreadsheet "Constrain Editor", as represented in Fig. 8.

pin assignments

Fig 8. Using the Constrain Editor for pin assignments available through the ispLEVER Classic project navigator.  

So that the final configuration file *.JED can be downloaded into the chip. This task is performed as shown in Fig. 9, by a chip programmer tool like the ispVM System from Lattice Semiconductor.

Programming

Fig 9. This is the ispVM System tool to be used for chip programing. The development board is connected to the computer using a simple USB interface and the tool scans the hardware to detect which is the chip populating the board. Clicking GO the PLD is programmed in a few seconds.

For sPLD or CPLD technologies, the programming of the macrocells is permanent and only can be erased reprogramming he chip another time with the same or a different configuration.

For FPGA technologies, the programming of the LUT (look-up tables) is volatile, and the RAM is erased once unplugged from the power supply. Thus, usually boards contain a supportive EEPROM memory to save the FPGA configuration rewriting the RAM every time the board is powered.  

 

Finally, we can experiment with the prototype represented in Fig. 10 in order to see whether all the specifications has been met, as shown in this recording. Many times the real circuit, as it was in the simulations, does not fully work, and so, a design loop (Visio) must be started again to modify schematics, rewrite VHDL code and synthesise and program again.

Prototype

Fig 10. This is a picture of the scanning keyboard running on a Lattice ispMACH4128V CPLD target chip (click to zoom).

 

Other similar projects on sequential circuits

- Exams, questions, problems and projects

- This project is complemented using materials from P8 on the design of the CLK_Generator component so that the CLK frequency can be derived from a quartz crystal oscillator populating the training board.

- This is an example of product enhancement: a 16-key matrix encoder with handshake signals.

Other materials of interest

- General ideas on FSM. (AMD, 1993).

- An application note on how to design safe FSM, the concept to prevent that a machine "hangs" being unable to get back to a valid state.

- At this stage it is recommended to read books in digital electronics to see how the stuff  in sequential systems is explained and which are the differences with respect the methodologies in CSD.

- Here you are a commercial chip from SILEGO, a company specialised in "asynchronous" state machines (ASM) architectures  which is very similar to the system we are dealing with.  Naturally, we can implement the functionality of the chip in our PIC or Atmel microcontroller in the project P12 as an example of microcontroller application. 

Silego

Fig 11. Block diagram of the SILEGO GreenPAK chip that performs the I2C interface between a keypad and a microcontroller.